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| 型号： | NCP1910A65DWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/37页 |
| 文件大小： | 0K |
| 描述： | IC COMBO CTLR ATX 24-SOIC |
| 标准包装： | 1 |
| 模式： | 连续导电（CCM） |
| 频率 - 开关： | 245 kHz |
| 电流 - 启动： | 100µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽）23 引线 |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 标准包装 |
| 其它名称： | NCP1910A65DWR2GOSDKR |
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NCP1910
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to +125 ° C, Max T J = 150 ° C,
V CC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
POWER FACTOR CORRECTION
REGULATION BLOCK
V PREF
I EA
G EA
I B
V CTRL
V CTRL(max)
V CTRL(min)
D V CTRL
V OUT L / V PREF
H OUT L / V PREF
I VLD + I EA
PFC Voltage reference
Error Amplifier Current Capability
Error Amplifier Gain
Bias Current @ V FB = V PREF
Maximum Control Voltage @ V FB = 2 V
Minimum Control Voltage @ V FB = 3 V
D V CTRL = V CTRL(max) ? V CTRL(min)
Ratio (V OUT Low Detect Threshold / V PREF ) (Note 4)
Ratio (V OUT Low Detect Hysteresis / V PREF )
Source Current when (V OUT Low Detect) is activated
?
10
?
9
10
10
10
?
?
10
2.425
?
100
0
?
?
2.7
94
?
190
2.5
$ 30
200
?
3.6
0.6
3
95
0.5
230
2.575
?
300
0.3
?
?
3.3
96
?
260
V
m A
m S
m A
V
%
%
m A
CURRENT SENSE
V S
I CS(OCP)
Current Sense Pin Offset Voltage, (I CS = 100 m A)
Over ? Current Protection Threshold
14
14
?
185
10
200
?
215
mV
m A
POWER LIMIT
I CS x V LBO
I CS(OPL1)
I CS(OPL2)
Over Power Limitation Threshold
Over ? Power Current Threshold (V LBO = 1.8 V, V M = 0 V)
Over ? Power Current Threshold (V LBO = 3.6 V, V M = 0 V)
?
?
215
119
56
275
153
75
335
187
99
m VA
m A
PULSE WIDTH MODULATION
F PSW
F PSW(fold)
DC Pmax
DC Pmin
V CTRL(fold)
V CTRL(foldend)
V fold(max)
PFC Switching Frequency
Minimum Switching Frequency (V fold = 1.5 V, V CTRL = V CTRL(min) +
0.1 V)
Maximum PFC Duty Cycle
Minimum PFC Duty Cycle
V CTRL pin voltage to start frequency foldback (V fold = 1.5 V)
V CTRL pin voltage as frequency foldback reducing to the minimum
(F PSW = F PSW(fold) , V fold = 1.5 V)
Maximum internal fold voltage (Note 4)
18
18
18
18
10
10
?
58
34
?
?
1.8
1.4
1.97
65
39
97
?
2
1.6
2
72
43
?
0
2.2
1.8
2.03
kHz
kHz
%
%
V
V
V
LINE BROWN ? OUT DETECTION
V LBOT
I LBOH
t LBO(blank)
t LBO(window)
V LBO(clamp)
V LBOH
I LBO(clamp)
V LBO(PNP)
Line Brown ? Out Voltage Threshold
Line Brown ? Out Hysteresis Current Source
Line Brown ? Out Blanking Time
Line Brown ? Out Monitoring Window (Note 4)
LBO Pin clamped voltage if V BO < V LBOT during t LBO(BLANK) (I LBO =
100 m A)
Hysteresis (V LBOT – V LBO(clamp) ) (Note 4)
Current Capability of LBO
LBO pin voltage when clamped by the PNP Transistor (I LBO =
100 m A)
12
12
?
?
12
12
12
12
0.96
6
25
25
?
10
100
0.4
1.00
7
50
50
980
35
?
0.7
1.04
8
75
75
?
60
?
0.9
V
m A
ms
ms
mV
mV
m A
V
3. In normal operation, when the power supply is un ? plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,
when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge
slope. However, if for an unknown reason the PFC is disabled (fault, short ? circuit), the PG pin immediately opens and if sufficient voltage
is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.
4. Guaranteed by design.
http://onsemi.com
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