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参数资料
| 型号： | NCP1910A65DWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/37页 |
| 文件大小： | 0K |
| 描述： | IC COMBO CTLR ATX 24-SOIC |
| 标准包装： | 1 |
| 模式： | 连续导电（CCM） |
| 频率 - 开关： | 245 kHz |
| 电流 - 启动： | 100µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽）23 引线 |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 标准包装 |
| 其它名称： | NCP1910A65DWR2GOSDKR |
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NCP1910
SS
Rt
PG out
ON/OFF
BO adj.
Vref
PG adj.
OVP2
FB
VCTRL
VM
LBO
1
24
Vboot
MU
Bridge
ML
V CC
DRV
GND/PGND
Skip/AGND
CS/FF
CS
Fold
Figure 1. Pin Connections
PIN DESCRIPTION
Pin N 5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
Pin Name
SS
Rt
PG out
on/off
BO adj.
Vref
PG adj.
OVP2
FB
V CTRL
V M
LBO
Fold
CS
CS/FF
Skip/AGND
GND/PGND
DRV
V CC
ML
Bridge
MU
V boot
Function
Soft ? start
The LLC feedback pin
The open ? collector power good signal
Remote control
Brown ? out adjustment
The 5 V reference pin
The power good trip level
Redundant OVP
PFC feedback
PFC Error amplifier output
PFC current amplifier output
PFC line input voltage sensing
PFC fold back
PFC current sense
Fast ? fault input
Skip (B)/AGND (A)
GND (B)/PGND (A)
PFC drive signal
The controller supply
Lower ? side MOSFET
Half ? bridge
Upper ? side MOSFET
Bootstrapped Vcc
Pin Description
A capacitor to ground sets the LLC soft ? start duration
A resistive arrangement sets the maximum and minimum
switching frequencies with opto coupler ? based feedback
capabilities.
This pin is low when V bulk is ok, opens when V bulk passes
below a level adjusted by PGadj pin.
When pulled low, the circuit operates: the PFC starts first and
once FB is in regulation, the LLC is authorized to work. When
left open, the controller is in idle mode.
This pin sets the on and off levels for the PFC powering the
LLC converter
This pin delivers a stable voltage for threshold adjustments
From the Vref pin, a dc level sets the trip point for the PFC
bulk voltage at which the PG out signal is down.
A fully latched OVP monitoring the PFC bulk independently
from FB pin.
Monitors the boost bulk voltage and regulates it. It also serves
as a quick auto ? recovery OVP
PFC error amplifier compensation pin
A resistor to ground sets the maximum power level
Line feed forward and PFC brown ? out
This pin selects the power level at which the frequency starts
to reduce gradually.
This pin senses the inductor current and also programs the
maximum sense voltage excursion
When pulled above 1 V, the LLC stops and re ? starts via a full
soft ? start sequence.
This pin is either used as the analog GND for the signal circuit
(A) or for skip operation (B).
The controller ground for the driving loop (A) or the lump
ground pin for all circuits (B)
The driving signal to the PFC power MOSFET
The power supply pin for the controller, 20 V max.
Drive signal for the lower side half ? bridge MOSFET
This pin connects to the LLC half ? bridge
Drive signal for the upper side half ? bridge MOSFET
The bootstrapped V CC for the floating driver
http://onsemi.com
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