参数资料
型号: NCP3020ADR2G
厂商: ON Semiconductor
文件页数: 10/23页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
标准包装: 1
PWM 型: 电压模式
输出数: 1
频率 - 最大: 360kHz
占空比: 84%
电源电压: 4.7 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 标准包装
其它名称: NCP3020ADR2GOSDKR
NCP3020A, NCP3020B, NCV3020A, NCV3020B
OOV and OUV
The output voltage of the buck converter is monitored at
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figures 22 and 23. All comparator outputs are
ignored during the soft ? start sequence as soft ? start is
regulated by the OTA and false trips would be generated.
After the soft ? start period has ended, if the feedback is
below the reference voltage of comparator 2 (V FB < 0.45 V),
the output is considered “undervoltage” and the device will
initiate a restart. When the feedback pin voltage rises
between the reference voltages of comparator 1 and
comparator 2 (0.45 < V FB < 0.75), then the output voltage
is considered “Power Good.” Finally, if the feedback voltage
is greater than comparator 1 (V FB > 0.75 V), the output
voltage is considered “overvoltage,” and the device will
latch off. To clear a latch fault, input voltage must be
recycled. Graphical representation of the OOV and OUV is
shown in Figures 24 and 25.
Soft Start Complet e
Vref*125%
Comparator 1
Restart
LOGIC
FB
Latch off
Vref = 0.6 V
Vref*75%
Comparator 2
Figure 22. OOV and OUV Circuit Diagram
Hysteresis = 5 mV
OOVP & Power Good = 0
Voov = Vref * 125%
Power Not good High
Power Good = 1
Vref = 0.6 V
Power Good = 1
Hysteresis = 5 mV
OUVP & Power Good = 0
Figure 23. OOV and OUV Window Diagram
http://onsemi.com
10
Power Not Good Low
Vouv = Vref * 75%
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