- 您现在的位置：买卖IC网 > PDF目录15054 > NCP5211DR2G (ON Semiconductor)IC REG CTRLR BUCK PWM 14-SOIC PDF资料下载
参数资料
| 型号： | NCP5211DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 14-SOIC |
| 产品变化通告： | Product Obsolescence 19/Dec/2008 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 900kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP5211
V FFB Feedback Selection
To take full advantage of the V 2 control scheme, a small
amount of output ripple must be fed back to the V FFB pin,
typically 50 mV. For most application, this requirement is
simple to achieve and the V FFB can be connected directly to
the V FB pin. There are some application that have to meet
stringent load transient requirements. One of the key factor
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. This situation could result in increase noise
sensitivity and a potential for loop instability. In applications
where the output ripple is not sufficient, the performance of
the NCP5211 can be improved by adding a fixed amount
external ramp compensation to the V FFB pin. Refer to Figure
7, the amount of ramp at the V FFB pin depends on the switch
Current Sense Component Selection
The current limit threshold is set by sensing a 60 mV
voltage differential between the IS+ and IS? pins. Referring
to Figure 8, the time constant of the R2,C1 filter should be
set larger than the L/R1 time constant under worst case
tolerances, to prevent overshoot in the sensed voltage and
tripping the current limit too low. Resistor R3 of value equal
to R2 is added for bias current cancellation. R2 and R3
should not be made too large, to reduce errors from bias
current offsets. For typical L/R time constants, a 0.1 m F
capacitor for C1 will allow R2 to be between 1.0 k and 10 k W .
The current limit without R4 and R5, which are optional, is
given by 60 mV/R1, where R1 is the internal resistance of the
inductor, obtained from the manufacturer. The addition of R5
can be used to decrease the current limit to a value given by:
node Voltage, Feedback Voltage, R1 and C2.
Vramp + (Vsw * VFB) ton (R1
C2)
ILIM + (60 mV * (VOUT R3 (R3 ) R5)) R1
where V OUT is the output voltage.
where:
Vramp = amount of ramp needed;
Vsw = switch note voltage;
V FB = voltage feedback, 1 V;
ton = switch on?time.
To minimize the lost in efficiency R1 resistance should be
large, typically 100 k or larger. With R1 chosen, C2 can be
determined by the following;
Similiarly, omitting R5 and adding R4 will increase the
current limit to a value given by:
ILIM + 60 mV R1 (1 ) R2 R4)
Essentially, R4 or R5 are used to increase or decrease the
inductor voltage drop which corresponds to 60 mV at the IS+
and IS? pins.
C2 + (Vsw * VFB) ton (R1 Vramp)
C1 is used as a bypass capacitor and its value should be
equal to or greater than C2.
IS?
60 mV Trip
R5
R3
Vsw
IS+
R1
R2
C1
C1
C2
R2
1.0 k
V FFB
V FB
Switching
Node
R4
L1
R1
L
Figure 8. Current Limit
V OUT
Figure 7. Small RC Filter Providing the Proper Voltage
Ramp at the Beginning of Each On?Time Cycle
Maximum Frequency Operation
The minimum pulse width may limit the maximum
operating frequency. The duty factor, given by the output/input
voltage ratio, multiplied by the period determines the pulse
width during normal operation. This pulse width must be
greater than 200 ns, or duty cycle jitter could become
excessive. For low pulse widths below 300 ns, external slope
compensation should be added to the V FFB pin to increase the
Boost Component Selection for Upper FET Gate Drive
The boost (BST) pin provides for application of a higher
voltage to drive the upper FET. This voltage may be provided
by a fixed higher voltage or it may be generated with a boost
capacitor and charging diode, as shown in Figure 10. The
voltage in the boost configuration would be the summation of
the voltage from the charging diode and the output voltage
swing. Care must be taken to keep the peak voltage with
respect to ground less than 20 V peak. The capacitor should be
large enough to drive the capacitance of the top FET.
PWM ramp signal and improve stability. 50 mV of added ramp
at the V FFB pin is typically enough.
http://onsemi.com
11
相关PDF资料 |
PDF描述 |
|---|---|
| GEM22DTBT-S273 | CONN EDGECARD 44POS R/A .156 SLD |
| GEM22DTAT-S273 | CONN EDGECARD 44POS R/A .156 SLD |
| GBA30DRMZ-S273 | CONN EDGECARD 60POS .125 SQ WW |
| EMM08DRST-S273 | CONN EDGECARD 16POS DIP .156 SLD |
| EBM22DRST-S273 | CONN EDGECARD 44POS DIP .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NCP5212A | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Single Synchronous Step-Down Controller |
| NCP5212A_09 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Single Synchronous Step-Down Controller |
| NCP5212AGEVB | 功能描述:BOARD EVAL NCP5212A RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
| NCP5212AMNTXG | 功能描述:DC/DC 开关控制器 SYNC STEP DOWN CTRL RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5212T | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Single Synchronous Step-Down Controller |
发布紧急采购，3分钟左右您将得到回复。