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| 型号： | NCP5211DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 14-SOIC |
| 产品变化通告： | Product Obsolescence 19/Dec/2008 |
| 标准包装： | 2,500 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 900kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
NCP5211
the design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
V GS_TH
I D
V GATE
non?overlap time of the gate drivers.
Q GS1
Q GS2
Q GD
V DRAIN
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)
) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where I RMS,CNTL is the RMS value of the trapezoidal
current in the control MOSFET:
IRMS,CNTL + D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN
) ILo,MIN2) 3]1 2
I Lo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAX 2 ) D ILo 2
I Lo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX 2 * D ILo 2
I O,MAX is the maximum converter output current.
D is the duty cycle of the converter:
D + VOUT VIN
D I Lo is the peak?to?peak ripple current in the output
inductor of value Lo:
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
R DS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q switch is the post gate threshold portion of the
gate?to?source charge plus the gate?to?drain charge. This
may be specified in the data sheet or approximated from the
gate?charge curve as shown in the Figure 5.
Qswitch + Qgs2 ) Qgd
Figure 5. MOSFET Switching Characteristics
I g is the output current from the gate driver IC.
V IN is the input voltage to the converter.
f sw is the switching frequency of the converter.
Q G is the MOSFET total gate charge to obtain R DS(on) .
Commonly specified in the data sheet.
V g is the gate drive voltage.
Q RR is the reverse recovery charge of the lower MOSFET.
Q oss is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non?overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
IRMS,SYNCH + 1 * D
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
where:
Vf diode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non?overlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
q T t (TJ * TA) PD
where;
q T is the total thermal impedance ( q JC + q SA ).
q JC is the junction?to?case thermal impedance of the
MOSFET.
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