参数资料
| 型号： | NCP5322ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/31页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 3.3V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5322ADWR2OSCT |
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NCP5322A
when the load current is removed. For low current
applications a droop resistor can provide fast accurate adaptive
positioning. However, at high currents the loss in a droop
resistor becomes excessive. For example; in a 50 A converter
a 1 m W resistor to provide a 50 mV change in output voltage
between no load and full load would dissipate 2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond to changes in load current.
Figure 14 shows how adaptive positioning works. The
waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 14. Adaptive Positioning
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to the application diagram in Figure 1). To set the no?load
positioning, a resistor is placed between the output voltage
and V FB pin. The V FB bias current will develop a voltage
across the resistor to adjust the no?load output voltage. The
V FB bias current is dependent on the value of R OSC as shown
in the datasheet.
During no load conditions the V DRP pin is at the same
voltage as the V FB pin, so none of the V FB bias current flows
through the V DRP resistor. When output current increases
the V DRP pin increases proportionally and the V DRP pin
current offsets the V FB bias current and causes the output
voltage to decrease.
The response during the first few microseconds of a load
transient are controlled primarily by power stage output
impedance and the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
current signal size is too large or the error amp too slow there
will be a long transition to the final voltage after a transient.
This will be most apparent with lower capacitance output
filters.
Error Amp Compensation & Tuning
The transconductance error amplifier requires a capacitor
(C CMP1 in the Applications Diagram) between the COMP
pin and GND. This capacitor stabilizes the transconductance
error amplifier. Values less than 1 nF may cause oscillations
of the COMP voltage. These oscillations will increase the
output voltage jitter.
The capacitor (C AMP ) between the COMP pin and the
inverting error amplifier input (the V FB pin) and the parallel
combination of the resistors R FBK1 and R DRP1 determine the
bandwidth of the error amplifier. The gain of the error
amplifier crosses 0 dB at a high enough frequency to give a
quick transient response, but well below the switching
frequency to minimize ripple and noise on the COMP pin.
A capacitor in parallel with the V FB resistor (C FBK2 ) adds
a zero to boost phase near the crossover frequency to
improve loop stability.
Setting?up and tuning the error amplifier is a three step
process. First, the no?load and full?load adaptive voltage
positioning (AVP) are set using R FBK1 and R DRP1 ,
respectively. Second, the current sense time constant and
error amplifier gain are adjusted with R CSn and C AMP while
monitoring V OUT during transient loading. Lastly, the
peak?to?peak voltage ripple on the COMP pin is examined
when the converter is fully loaded to insure low output
voltage jitter. The details of this process are covered in the
Design Procedure section.
Undervoltage Lockout (UVLO)
The controller has undervoltage lockout functions
connected to two pins. One, intended for the logic and
low?side drivers, with approximately a 4.2 V turn?on
threshold is connected to the V CCL pin. A second, for the
high side drivers, with approximately a 1.875 V threshold,
is connected to the V CCH1 pin.
The UVLO threshold for the high side drivers varies with
the part type. In many applications this function will be
disabled or will only check that the applicable supply is on
? not that is at a high enough voltage to run the converter. See
individual datasheets for more information on UVLO.
Soft Start Enable, and Hiccup Mode
A capacitor between the Soft Start pin and GND controls
Soft Start and Hiccup mode slopes. A 0.1 m F capacitor with
the 30 m A charge current will allow the output to ramp up at
0.3 V/ms or 1.6 V in 5.3 ms at start?up.
When a fault is detected due to an overcurrent condition
the converter will enter a low duty cycle hiccup mode.
During hiccup mode the converter will not switch from the
time a fault is detected until the Soft Start capacitor has
discharged below the Soft Start Discharge Threshold and
then charged back up above the Channel Start Up Offset.
The Soft Start pin will disable the converter when pulled
below the maximum Soft Start Discharge Threshold
(nominally 0.27 V).
Power Good (PWRGD)
The open?collector Power Good (PWRGD) pin is driven
by a “window?comparator” monitoring V CORE . This
comparator will transition HIGH if V CORE is within ± 12%
of the nominal VID setting. After a 120 m s delay, the
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