参数资料
| 型号： | NCP5322ADWR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/31页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH STEPDWN 28SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 3.3V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5322ADWR2OSCT |
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NCP5322A
comparators output will saturate the open?collector output
transistor and the PWRGD pin will be pulled LOW.
Layout Guidelines
6.
and GATE traces, away from the R OSC pin and
resistor.
Place the Soft Start capacitor (C SS ) near the Soft
Start pin.
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multi?layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to route the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
The current sense signals are typically tens of milli?volts.
Noise pick?up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as the switch node and gate drive signals. If the
current signals are taken from a location other than directly
at the inductor any additional resistance between the
pick?off point and the inductor appears as part of the
inherent inductor resistances and should be considered in
design calculations. The capacitors for the current feedback
networks should be placed as close to the current sense pins
as practical. After placing the NCP5322A control IC, follow
these guidelines to optimize the layout and routing:
1. Place the 1 m F power supply bypass (ceramic)
capacitors close to their associated pins: V CCL ,
V CCH1 (and/or V CCH2 ), V CCL1 (and/or V CCL2 ).
2. Place the MOSFETs to minimize the length of the
Gate traces. Orient the MOSFETs such that the
Drain connections are away from the controller and
the Gate connections are closest to the controller.
3. Place the components associated with the internal
error amplifier (R FBK1 , C FBK2 , C AMP , R CMP1 ,
C CMP1 , R DRP1 ) to minimize the trace lengths to
the pins V FB , V DRP and COMP.
4. Place the current sense components (R CS1 , R CS2 ,
C CS1 , C CS2 , R CSREF , C CSREF ) near the CS1, CS2,
and CS REF pins.
5. Place the frequency setting resistor (R OSC ) close to
the R OSC pin. The R OSC pin is very sensitive to
noise. Route noisy traces, such as the SWNODEs
7.
8.
9.
10.
11.
12.
13.
14.
15.
Place the MOSFETs and output inductors to reduce
the size of the noisy SWNODEs. There is a trade?
off between reducing the size of the SWNODEs
for noise reduction and providing adequate
heat?sinking for the synchronous MOSFETs.
Place the input inductor and input capacitor(s) near
the Drain of the control (upper) MOSFETs. There
is a trade?off between reducing the size of this
node to save board area and providing adequate
heat?sinking for the control MOSFETs.
Place the output capacitors (electrolytic and ceramic)
close to the processor socket or output connector.
The trace from the SWNODEs to the current sense
components (R CS1 , R CS2 ) will be very noisy.
Route this away from more sensitive, low?level
traces. The Ground layer can be used to help
isolate this trace.
The Gate traces are very noisy. Route these away
from more sensitive, low?level traces. Keep each
Gate signal on one layer and insure that there is an
uninterrupted return path directly below the Gate
trace. The Ground layer can be used to help isolate
these traces.
Don’t “daisy chain” connections to Ground from
one via. Allow each connection to Ground to have
its own via as close to the component as possible.
Use a slot in the ground plane from the bulk output
capacitors back to the input power connector to
prevent high currents from flowing beneath the
control IC. This slot should extend length?wise
under the control IC and separate the connections
to “signal ground” and “power ground.” Examples
of signal ground include the capacitors at COMP,
CS REF , Soft?Start (SS), V CCL , and REF, the
resistors at R OSC and I LIM , and the LGND pin to
the controller. Examples of power ground include
the capacitors to V CCH1 (and/or V CCH2 ) and
V CCL1 (and/or V CCL2 ), the Source of the
synchronous MOSFET, and the GND1 and GND2
pins of the controller.
The CS REF sense point should be equidistant
between the output inductors to equalize the PCB
resistance added to the current sense paths. This
will insure acceptable current sharing. Also, route
the CS REF connection away from noisy traces such
as the SWNODEs and GATE traces. If noise from
the SWNODEs or GATE signals capacitively
couples to the CS REF trace the external ramps will
be very noisy and voltage jitter will result.
Ideally, the SWNODEs are exactly the same shape
and the current sense points (connections to R CS1
http://onsemi.com
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