参数资料
| 型号： | NCP5331FTR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 27/36页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 2PH PWM DRV 32LQFP |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1 |
| 应用： | 控制器，AMD Athlon? |
| 输入电压： | 9 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5331FTR2OSCT |
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NCP5331
5. MOSFET and Heatsink Selection
Power dissipation, package size, and thermal solution drive
MOSFET selection. To adequately size the heat sink, the
design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
V GS_TH
I D
V GATE
will exhibit only conduction losses because it switches into
Q GS1
Q GS2
Q GD
V DRAIN
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
nonoverlap time of the gate drivers.
Figure 32. MOSFET Switching Characteristics
For the upper or control MOSFET, the power dissipation
can be approximated from
Qswitch + Qgs2 ) Qgd
(25)
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)
(19)
I g is the output current from the gate driver IC.
V IN is the input voltage to the converter.
f sw is the switching frequency of the converter.
) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON, while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
I RMS,CNTL is the rms value of the trapezoidal current in the
Q RR is the reverse recovery charge of the lower MOSFET.
Q oss is the sum of all the MOSFET output charges.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
(26)
) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON, and the second term represents the
diode losses that occur during the gate nonoverlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of
control MOSFET.
IRMS,SYNCH + [(1 * D)
(27)
IRMS,CNTL + [D @ (ILo,MAX2 ) ILo,MAX @ ILo,MIN (20)
) ILo,MIN2) 3]1 2
@ (ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
Vf diode is the forward voltage of the MOSFET’s intrinsic
I Lo,MAX is the maximum output inductor current.
ILo,MAX + IO,MAX 2 ) D ILo 2
I Lo,MIN is the minimum output inductor current.
ILo,MIN + IO,MAX 2 * D ILo 2
I O,MAX is the maximum converter output current.
D is the duty cycle of the converter.
(21)
(22)
diode at the converter output current.
t_nonoverlap is the nonoverlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
D + VCORE VIN
(23)
q T t (TJ * TA) PD
(28)
D ILo + (VIN * VCORE) @ D (Lo @ fSW)
D I Lo is the peak?to?peak ripple current in the output
inductor of value L o .
(24)
R DS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q switch is the post gate threshold portion of the
gate?to?source charge plus the gate?to?drain charge. This
may be specified in the data sheet or approximated from the
gate?charge curve as shown in the Figure 32.
where
q T
q JC
q SA
T J
T A
is the total thermal impedance ( q JC + q SA ),
is the junction?to?case thermal impedance of
the MOSFET,
is the sink?to?ambient thermal impedance of
the heatsink assuming direct mounting of the
MOSFET (no thermal “pad” is used),
is the specified maximum allowed junction
temperature,
is the worst case ambient operating temperature.
http://onsemi.com
27
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| NCP5331FTR2G | 功能描述:DC/DC 开关控制器 2 Phase Buck w/Gate Drivers for Athlon RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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| NCP5332ADW | 功能描述:DC/DC 开关控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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