参数资料
型号: NJ88C33/MA/MP
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 150 MHz, PDSO14
封装: 0.150 INCH, PLASTIC, MS-012AB, SOIC-14
文件页数: 14/15页
文件大小: 449K
代理商: NJ88C33/MA/MP
NJ88C33
7
Address and Sub-Address Formats
The correct addressing sequence for the NJ88C33 is
shown below.
The START condition is followed by the
address byte, the acknowledge from the NJ88C33, the sub-
address byte, another acknowledge then the associated data.
The correct values for each address and sub-address are
listed, together with the message selection options.
S = Start
St = Stop
A = Acknowledge
P = Programmable (as shown)
x = Don't care
Data Formats
Each of the data formats should be preceded contiguously
by the addressing sequence given above.
R counter : single or dual modulus
Status : single or dual modulus
N counter : single modulus
A/N counters : dual modulus
1
2
3
4
5
6
7
8
PORT = low
Counters off (1)
FI and RI off (2)
PD = polarity negative
PD bias = 0.625mA
f
VD = RI/2
Doubler off
MOD = push-pull
PORT = high
Counters on
FI and RI on
PD = polarity positive
PD bias = 2.5mA
f
VD = RI/4
Doubler on (3)
MOD = open drain
Status Byte
Bit
1
0
NOTES
1. In this standby mode the counters are disabled but the
voltage doubler and I2C interface can both function.
2. In this standby mode the FI and RI preamplifiers are
disabled, which stops the counters and the voltage doubler.
The I2C interface still operates.
3. The voltage doubler should only be used when V
DD ≤ 3.0V
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