参数资料
型号: NOIL1SM0300A-WWC
厂商: ON Semiconductor
文件页数: 10/30页
文件大小: 0K
描述: IC IMAGE SENSOR LUPA300 48LLC
标准包装: 1
系列: LUPA300
象素大小: 9.9µm x 9.9µm
有源象素阵列: 640H x 480V
每秒帧数: 250
电源电压: 2.5 V,3.3 V
类型: CMOS 成像
封装/外壳: 48-LCC
供应商设备封装: 48-LCC(14.22x14.22)
包装: 托盘
NOIL1SM0300A
Biasing
Table 9 summarizes the biasing signals required to drive
this image sensor. For optimization reasons of the biasing of
Table 9. OVERVIEW OF BIAS SIGNALS
the column amplifiers with respect to power dissipation,
several biasing resistors are required. This optimization
results in an increase of signal swing and dynamic range.
Signal [1]
ADC_BIAS
PRECHARGE_BIAS
BIAS_PGA
BIAS_FAST
BIAS_SLOW
BIAS_COL
Comment
Connect with 10 k W to V ADC and decouple with 100n to GND ADC
Connect with 68 k W to V PIX and decouple with 100 nF to
GND DRIVERS
Biasing of amplifier stage. Connect with 110 k W to V DDA and de-
couple with 100 nF to GND A
Biasing of columns. Connect with 42 k W to V DDA and decouple with
100 nF to GND A
Biasing of columns. Connect with 1.5 M W to V DDA and decouple
with 100 nF to GND A
Biasing of imager core. Connect with 500 k W to V DDA and decouple
with 100 nF to GND A
Related Module
ADC
Pixel array precharge
PGA
Column amplifiers
Column amplifiers
Column amplifiers
DC ? Level
693 mV
567 mV
650 mV
750 mV
450 mV
508 mV
1. Each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation.
Digital Signals
Depending on the operation mode (master or slave), the
pixel array of the image sensor requires different digital
Table 10. OVERVIEW OF BIAS SIGNALS
control signals. The function of each of the signals is shown
in Table 10.
Signal
LINE_VALID
FRAME_VALID
INT_TIME_3
INT_TIME_2
INT_TIME_1
RESET_N
CLK
SPI_ENABLE
SPI_CLK
SPI_DATA
I/O
Digital output
Digital output
Digital I/O
Digital I/O
Digital I/O
Digital input
Digital input
Digital input
Digital input
Digital I/O
Comments
Indicates when valid data is at the outputs. Active high
Indicates when a valid frame is readout. Active high
In master mode: Output to indicate the triple slope integration time.
In slave mode: Input to control the triple slope integration time.
Active high
In master mode: Output to indicate the dual slope integration time.
In slave mode: Input to control the dual slope integration time.
Active high
In master mode: Output to indicate the integration time.
In slave mode: Input to control integration time.
Active high
Sequencer reset. Active low
Readout clock (80 MHz), sine or square clock
Enable of the SPI
Clock of the SPI. (Max. 20 MHz)
Data line of the SPI. Bidirectional pin
http://onsemi.com
10
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