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| 型号： | NOIL1SM0300A-WWC |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/30页 |
| 文件大小： | 0K |
| 描述： | IC IMAGE SENSOR LUPA300 48LLC |
| 标准包装： | 1 |
| 系列： | LUPA300 |
| 象素大小： | 9.9µm x 9.9µm |
| 有源象素阵列： | 640H x 480V |
| 每秒帧数： | 250 |
| 电源电压： | 2.5 V，3.3 V |
| 类型： | CMOS 成像 |
| 封装/外壳： | 48-LCC |
| 供应商设备封装： | 48-LCC（14.22x14.22） |
| 包装： | 托盘 |
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NOIL1SM0300A
Table 12. INTERNAL REGISTERS
9 (1001)
Address
7:0
Bits
VBLACK
Name
Description
DAC input for vblack
Default <7:0>: 01101011
10 (1010)
7:0
VOFFSET
DAC input for voffset
Default <7:0>: 01010101
11 (1011)
11:0
ANA_IN_ADC
Activate analog ADC input
Default <11:0>: 000011110000
4
4
4
sel_test_path
sel_path
bypass_mux
Selection of analog test path
Selection of normal analog path
Bypass of digital 4 to 1 mux
12 (1100)
11:0
PGA_SETTING
PGA settings
Default <11:0>: 111110110000
4
1
1
1
4
1
gain_pga
unity_pga
sel_uni
enable_analog_in
enable_adc
sel_calib_fast
Gain settings PGA
PGA unity amplification
Preamplification of 0.5 (0: enabled)
Activate analog input
Put separate ADCs in standby
Select fast calibration of PGA
13 (1101)
14 (1110)
15 (1111)
11:0
11:0
8:0
CALIB_ADC <11:0>
CALIB_ADC <23:12>
CALIB_ADC <32:24>
Calibration word of the ADCs
Default:
calib_adc<11:0>:101011011111
calib_adc<23:12>:011011011011
calib_adc<32:24>:000011011011
Detailed Description of the Internal Registers
The registers should only be changed during FOT (when
frame valid is low).
These registers should only be changed during RESET_N
is low:
? Mastermode register
? Granularity register
Sequencer Register <10:0>
The sequencer register is an 11 bit wide register that
controls all of the sequencer settings. It contains several
”sub-registers”.
Mastermode (1 bit)
This bit controls the selection of mastermode/slavemode.
The sequencer can operate in two modes: master mode and
slave mode. In master mode all the internal timing is
controlled by the sequencer, based on the SPI settings. In
slave mode the integration timing is directly controlled over
three pins, the readout timing is still controlled by the
sequencer.
1: Master mode (default)
0: Slave mode
Subsampling (1bit)
This bit enables/disables the subsampling mode.
Subsampling is only possible in Y direction and follows this
pattern:
? Read one, skip one: Y0Y0Y0Y0 …
By default, the subsampling mode is disabled.
Clock granularity (2 bits)
The system clock (80 MHz) is divided several times on
chip.
The clock, that drives the ”snapshot” or synchronous
shutter sequencer, can be programmed using the granularity
register. The value of this register depends on the speed of
your system clock.
11: > 80 MHz
10: 40-80 MHz (default)
01: 20-40 MHz
00: < 20 MHz
Enable analog out (1 bit)
This bit enables/disables the analog output amplifier.
1: enabled
0: disabled (default)
Calib_line (1bit)
This bit sets the calibration method of the PGA. Different
calibration modes can be set, at the beginning of the frame
and for every subsequent line that is read.
1: Calibration is done every line (default)
0: Calibration is done every frame (less row fixed pattern
noise)
http://onsemi.com
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