参数资料
型号: NOIL1SM0300A-WWC
厂商: ON Semiconductor
文件页数: 22/30页
文件大小: 0K
描述: IC IMAGE SENSOR LUPA300 48LLC
标准包装: 1
系列: LUPA300
象素大小: 9.9µm x 9.9µm
有源象素阵列: 640H x 480V
每秒帧数: 250
电源电压: 2.5 V,3.3 V
类型: CMOS 成像
封装/外壳: 48-LCC
供应商设备封装: 48-LCC(14.22x14.22)
包装: 托盘
NOIL1SM0300A
Startup Timing
On startup, VDDD should rise together with or before the
other supplies. The rise of VDDD should be limited to
1V/100 m s to avoid activation of the on chip ESD protection
circuitry.
During the rise of VDDD an on chip POR_N signal is
generated that resets the SPI registers to its default setting.
After VDDD is stable the SPI settings can be uploaded to
configure the sensor for future readout and light integration.
When powering on the VDDD supply, the RESET_N pin
should be kept low to reset the on chip sequencer and
addressing logic. The RESET_N pin must remain low until
all initial SPI settings are uploaded. RESET_N pin must
remain low for at least 500 ns after ALL supplies are stable.
The rising edge of RESET_N starts the on chip clock
division. The second rising edge of CLK after the rising edge
of RESET_N, triggers the rising edge of the core clock.
Some SPI settings can be uploaded after the core clock has
started.
RESET_N
POR_N
(internal)
System clock
(external)
Core clock
(internal)
Min 500ns
VDDD power
supply
POWER ON
?VDDD STABLE
SPI upload
INVALID
SPI upload
INVALID
SPI upload if required
Figure 23. Startup Timing
Sequencer Reset Timing
By bringing RESET_N low for at least 50 ns, the on chip
sequencer is reset to its initial state. The internal clock
division is restarted. The second rising edge of CLK after the
System
clock
(external)
rising edge of RESET_N the internal clock is restarted. The
SPI settings are not affected by RESET_N. If needed the SPI
settings can be changed during a low level of RESET_N.
RESET_N
Core clock
(internal)
Sync_Y
(internal)
Clock_Y
(internal)
Min 50 ns
Normal operation
INVALID
Figure 24. Sequencer Reset Timing
http://onsemi.com
22
Normal operation
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