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| 型号： | NOIL1SM0300A-WWC |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/30页 |
| 文件大小： | 0K |
| 描述： | IC IMAGE SENSOR LUPA300 48LLC |
| 标准包装： | 1 |
| 系列： | LUPA300 |
| 象素大小： | 9.9µm x 9.9µm |
| 有源象素阵列： | 640H x 480V |
| 每秒帧数： | 250 |
| 电源电压： | 2.5 V，3.3 V |
| 类型： | CMOS 成像 |
| 封装/外壳： | 48-LCC |
| 供应商设备封装： | 48-LCC（14.22x14.22） |
| 包装： | 托盘 |
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NOIL1SM0300A
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the Frame
Overhead Time (FOT) and the Row Overhead Time (ROT).
The frame period is calculated as follows
Frame period = FOT + Nr. Lines * (ROT + Nr. Pixels *
clock period)
Table 3. FRAME RATE PARAMETERS
Example: read out of the full resolution at nominal speed
(80 MHz pixel rate = 12.5 ns, GRAN<1:0>=10):
Frame period = 7.8 m s + (480 * (400 ns + 12.5 ns * 640)
= 4.039 ms => 247.6 fps.
In case the sensor operates in subsampling, the ROT is
enlarged with 8 clock periods.
FOT
ROT
Parameter
Comment
Frame Overhead Time
Row Overhead Time
Clarification
1200 clock periods for GRAN<1:0> = 11
624 clock periods for GRAN<1:0> = 10
336 clock periods for GRAN<1:0> = 01
192 clock periods for GRAN<1:0> = 00
48 clock periods for GRAN<1:0> = 11
32 clock periods for GRAN<1:0> = 10
24 clock periods for GRAN<1:0> = 01
20 clock periods for GRAN<1:0> = 00
Nr. Lines
Nr. Pixels
clock period
Windowing
Number of lines read out each frame
Number of pixels read out each line
1/80 MHz = 12.5 ns
line (every line can be addressed) in normal mode and 2 lines
Windowing is achieved by the SPI interface. The starting
point of the x- and y-address is uploadable, as well as the
window size. The minimum step size in the x-direction is 8
pixels (only multiples of 8 can be chosen as start/stop
addresses). The minimum step size in the y-direction is 1
Table 4. FRAME RATE PARAMETERS
in subsampling mode.
The window size in the x-direction is uploadable in
register NB_OF_PIX. The window size in the y-direction is
determined by the register FT_TIMER
Parameter
640 x 480
640 x 240
256 x 256
Frame Rate (fps)
247.5
488.3
1076
Frame Readout (us)
4038
2048
929
Comment
Subsampling
Windowing
Analog to Digital Converter
The sensor has four 10-bit pipelined ADC on board. The
ADCs are nominally operating at 20 Msamples/s. The input
range of the ADC is between 0.75 and 1.75V. The analog
Table 5. ADC PARAMETERS
Parameter
Specification
input signal is sampled at 2.1 ns delay from the rising edge
of the ADC clock.
The digital output data appears at the output at 5.5 cycles
later. This is at the 6th falling edge succeeding the sample
moment. The data is delayed by 3.7 ns with respect to this
falling edge. This is illustrated in Figure 6.
Data rate
Input range
Quantization
DNL
INL
20 Msamples/s
0.75 V ? 1.75 V
10 bit
Typ. < 0.3 LSB
Typ. < 0.7 LSB
http://onsemi.com
6
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