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参数资料
| 型号： | NT5DS32M8AW-75B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Double Data Rate SDRAM |
| 中文描述： | 256MB双数据速率SDRAM |
| 文件页数： | 16/78页 |
| 文件大小： | 1534K |
| 代理商： | NT5DS32M8AW-75B |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
16
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Deselect
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is
effectively deselected. Operations already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode reg-
ister descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle
and no bursts are in progress. A subsequent executable command cannot be issued until t
MRD
is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for
accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with
Auto Precharge) command must be issued and completed before opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic
level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if
the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column
location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The
bank(s) will be available for a subsequent row access a specified time (t
RP
) after the Precharge command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated
as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS32M8AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-75B | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 256Mb Double Data Rate SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5DS32M8AW-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8CS | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-5T | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-6K | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
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