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| 型号： | NT5DS32M8AW-75B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Double Data Rate SDRAM |
| 中文描述： | 256MB双数据速率SDRAM |
| 文件页数： | 47/78页 |
| 文件大小： | 1534K |
| 代理商： | NT5DS32M8AW-75B |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
47
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
Any
H
X
X
X
Deselect
NOP. Continue previous operation
1-6
L
H
H
H
No Operation
NOP. Continue previous operation
1-6
Idle
L
L
H
H
Active
Select and activate row
1-6
L
L
L
H
Auto Refresh
1-7
L
L
L
L
Mode Register Set
1-7
Row Active
L
H
L
H
Read
Select column and start Read burst
1-6, 10
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Deactivate row in bank(s)
1-6, 8
Read
(Auto Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
1-6, 10
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1-6, 8
L
H
H
L
Burst Terminate
Burst Terminate
1-6, 9
Write
(Auto Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
1-6, 10, 11
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Truncate Write burst, start Precharge
1-6, 8, 11
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
XSNR /
t
XSRD
has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t
RP
has been met.
Row Active:
A row in the bank has been activated, and t
RCD
has been met. No data bursts/accesses and no register accesses are in
progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:
Starts with registration of a Precharge command and ends when t
RP
is met. Once t
RP
is met, the bank is in the idle
state.
Row Activating:
Starts with registration of an Active command and ends when t
RCD
is met. Once t
RCD
is met, the bank is in the “row
active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t
RP
has been
met. Once t
RP
is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t
RP
has been
met. Once t
RP
is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing:
Starts with registration of an Auto Refresh command and ends when t
RFC
is met. Once t
RFC
is met, the DDR SDRAM is
in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t
MRD
has been met. Once t
MRD
is
met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when t
RP
is met. Once t
RP
is met, all banks is in the idle
state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
11. Requires appropriate DM masking.
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS32M8AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-75B | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 256Mb Double Data Rate SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5DS32M8AW-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8CS | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-5T | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-6K | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
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