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参数资料
| 型号： | OR3L225B7PS680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680 |
| 封装： | PLASTIC, BGAM-680 |
| 文件页数： | 11/77页 |
| 文件大小： | 873K |
| 代理商： | OR3L225B7PS680-DB |
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PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following three types of I/O ports are available.
CMOS input (P00, P07):
2
CMOS I/O (P01 to P06, port 1 to port 5, P64 to P67, port 7, port 12, port 13):
63
N-ch open-drain I/O (P60 to P63):
4
Total:
69
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00, P07
Input-only
P01 to P06
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 1
P10 to P17
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 2
P20 to P27
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 3
P30 to P37
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 4
P40 to P47
I/O port. Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
The test flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
LEDs can be driven directly.
Port 6
P60 to P63
N-ch open-drain I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by the mask option.
LEDs can be driven directly.
P64 to P67
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 7
P70 to P72
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 12
P120 to P127
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 13
P130, P131
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
相关PDF资料 |
PDF描述 |
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| OR3L225B7PS680I-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680 |
| OR3L225B8PS432-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432 |
| OR3L225B8PS680-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA680 |
| OR3L225B7BC432-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA432 |
| OR3L225B8BC432-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432 |
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