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参数资料
| 型号： | OR3L225B7PS680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680 |
| 封装： | PLASTIC, BGAM-680 |
| 文件页数： | 74/77页 |
| 文件大小： | 873K |
| 代理商： | OR3L225B7PS680-DB |
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76
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
相关PDF资料 |
PDF描述 |
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| OR3L225B7PS680I-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680 |
| OR3L225B8PS432-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432 |
| OR3L225B8PS680-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA680 |
| OR3L225B7BC432-DB | FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA432 |
| OR3L225B8BC432-DB | FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432 |
相关代理商/技术参数 |
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| OR3L225B8BM680-DB | 功能描述:FPGA - 现场可编程门阵列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3LP26B | 制造商:AGERE 制造商全称:AGERE 功能描述:Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR3LP26BBA352-DB | 功能描述:FPGA - 现场可编程门阵列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 现场可编程门阵列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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