参数资料
型号: OR3L225B7PS680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680
封装: PLASTIC, BGAM-680
文件页数: 35/77页
文件大小: 873K
代理商: OR3L225B7PS680-DB
40
PD78052, 78053, 78054, 78055, 78056, 78058
Data Sheet U12327EJ5V0DS00
(2)
PD78058
Main system clock: Ceramic resonator (TA = –40 to +85
°C)
Frequency
Recommended
Oscillation
Manufacturer
Product Name
Circuit Constant
Voltage Range
Remarks
(MHz)
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
Kyocera
PBRC4.19A
4.19
33
2.0
6.0
Corp.
PBRC4.19B
4.19
On-chip
2.0
6.0
On-chip capacitor
KBR-4.19MSA
4.19
33
2.0
6.0
KBR-4.19MKS
4.19
On-chip
2.0
6.0
On-chip capacitor
PBRC4.91A
4.91
33
2.0
6.0
PBRC4.91B
4.91
On-chip
2.0
6.0
On-chip capacitor
KBR-4.91MSA
4.91
33
2.0
6.0
KBR-4.91MKS
4.91
On-chip
2.0
6.0
On-chip capacitor
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
However, oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For
details, please contact directly the manufacturer of the resonator you will use.
Capacitance (TA = 25
°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input
CIN
f = 1 MHz
15
pF
capacitance
Unmeasured pins returned to 0 V.
I/O
CIO
f = 1 MHz
P01 to P06, P10 to P17,
15
pF
capacitance
Unmeasured pins returned to 0 V.
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131
P60 to P63
20
pF
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
相关PDF资料
PDF描述
OR3L225B7PS680I-DB FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA680
OR3L225B8PS432-DB FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432
OR3L225B8PS680-DB FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA680
OR3L225B7BC432-DB FPGA, 1444 CLBS, 166000 GATES, 266.4 MHz, PBGA432
OR3L225B8BC432-DB FPGA, 1444 CLBS, 166000 GATES, 333 MHz, PBGA432
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