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| 型号： | OR3T55 |
| 英文描述： | 3C and 3T Field-Programmable Gate Arrays |
| 中文描述： | 3C和3吨现场可编程门阵列 |
| 文件页数： | 136/210页 |
| 文件大小： | 4669K |
| 代理商： | OR3T55 |
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Lucent Technologies Inc.
31
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Inter-PLC Routing Resources
The inter-PLC routing is used to route signals between
PLCs. The routing segments occur in groups of ten,
and differ in the numbers of PLCs spanned. The x1
routing segments span one PLC, the x5 routing seg-
ments span five PLCs, the xH routing segments span
one-half the width (height) of the PLC array, and the xL
routing segments span the width (height) of the PLC
array. All types of routing segments run in both horizon-
tal and vertical directions.
Table 8 shows the groups of inter-PLC routing seg-
ments in each PLC. In the table, there are two rows/col-
umns for x1 lines. They are differentiated by a T for top,
B for bottom, L for left, and R for right. In the
ORCA
Foundry design editor representation, the horizontal x1
routing segments are located above and below the
PFU. The two groups of vertical segments are located
on the left side of the PFU. The xL and x5 routing seg-
ments only run below and to the left of the PFU, while
the xH segments only run above and to the right of the
PFU. The indexes specify individual routing segments
within a group. For example, the vx5[2] segment runs
vertically to the left of the PFU, spans five PLCs, and is
the third line in the 10-bit wide group.
PLCs are arranged like tiles on the
ORCA device.
Breaks in routing occur at the middle of the tile (e.g., x1
lines break in the middle of each PLC) and run across
tiles until the next break.
Figure 20 provides a global view of inter-PLC routing
resources across multiple PLCs.
x1 Routing Segments. There are a total of 40 x1 rout-
ing segments per PLC: 20 vertical and 20 horizontal.
Each of these are subdivided into two, 10-bit wide
buses: hx1T[9:0], hx1B[9:0], vx1L[9:0], and vx1R[9:0].
An x1 segment is one PLC long. If a signal net is longer
than one PLC, an x1 segment can be lengthened to n
times its length by turning on n – 1 CIPs. A signal is
routed onto an x1 route segment via the switching rout-
ing segments or BIDI routing segments which also
allows the x1 route segment to be connected to other
inter-PLC segments of different lengths. Corner turning
between x1 segments is provided through direct con-
nections, xSW segments, and xBID segments.
x5 Routing Segments. There are two sets of ten x5
routing segments per PLC. One set (vx5[9:0]) runs ver-
tically, and the other (hx5[9:0]) runs horizontally. Each
x5 segment traverses five PLCs before it is broken by a
CIP. Two x5 segments in each group break in each
PLC. The two that break are in an equivalent pair; for
example, x5[0] and x5[4]. The x5 segments that break
shift by one at the next PLC. For example, if hx5[0] and
hx5[4] are broken at the current PLC, hx5[1] and hx5[5]
will be broken at the PLC to the right of the current
PLC. There are direct connections to the BIDI routing
segments in the PLC at which the x5 segments break,
on both sides of the break. Signal corner turning is
enabled by CIPs in each PLC that allow the broken x5
segments to directly connect to the broken x5 seg-
ments that run in the orthogonal direction. x5 corner
turning can also be accomplished via the xSW and
xBID segments in a PLC. In addition, the x5 segments
are connected to the FINS and PFU outputs on a bit-
by-bit basis by the xSW segments. x5 segments can be
connected for signal runs in multiples of five PLCs, or
they can be combined with x1 and xH routing segments
for runs of varying distances.
Table 8. Inter-PLC Routing Resources
Horizontal
Routing
Segments
Vertical
Routing
Segments
Distance
Spanned
hx1U[9:0]
vx1R[9:0]
One PLC
hx1B[9:0]
vx1L[9:0]
One PLC
hx5[9:0]
vx5[9:0]
Five PLCs
hx5[9:0]
vx5[9:0]
Five PLCs
hxL[9:0]
vxL[9:0]
PLC Array
hxH[9:0]
vxH[9:0]
1/2 PLC Array
hCLK
vCLK
PLC Array
相关PDF资料 |
PDF描述 |
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| OR4E041BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E041BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
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| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
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相关代理商/技术参数 |
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| OR3T55-5BA256 | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-5BA256I | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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