Lucent Technologies Inc.
111
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
PLC Timing
Table 46. PFU Output MUX and Direct Routing Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C
< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C
< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
* This is general feedback using switching segments. See the combinatorial PFU timing table for softwired look-up table feedback timing.
SLIC Timing
Table 47. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C
< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C
< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
(TJ = 85 °C, VDD = min)
Symbol
Speed
Unit
-4
-5
-6
-7
Min
Max
Min
Max
Min
Max
Min
Max
PFU Output MUX (Fan-out = 1)
Output MUX Delay (F[7:0]/Q[7:0] to O[9:0])
Carry-out MUX Delay (COUT to O9)
Registered Carry-out MUX Delay (REGCOUT
to O8)
OMUX_DEL
COO9_DEL
RCOO8_DEL
—
0.50
0.34
—
0.39
0.26
—
0.35
0.24
—
0.28
0.18
ns
Direct Routing
PFU Feedback (xSW)*
PFU to Orthogonal PFU Delay (xSW to xSW)
PFU to Diagonal PFU Delay (xBID to xSW)
FDBK_DEL
ODIR_DEL
DDIR_DEL
—
1.74
2.21
2.69
—
1.41
1.77
2.19
—
1.48
1.75
2.53
—
1.14
1.39
1.98
ns
Parameter
(TJ = 85 °C, VDD = min)
Symbol
Speed
Unit
-4
-5
-6
-7
Min
Max
Min
Max
Min
Max
Min
Max
3-Statable BIDIs
BIDI Delay (BRx to BLx, BLx to BRx)
BIDI Delay (Ox to BRx, Ox to BLx)
BIDI 3-state Enable/Disable Delay (TRI to BL, BR)
BIDI 3-state Enable/Disable Delay
(BL, BR via DEC, TRI to BL, BR)
BUF_DEL
OBUF_DEL
TRI_DEL
DECTRI_DEL
—
0.84
0.72
2.55
3.59
—
0.70
0.61
1.90
2.65
—
0.94
0.87
1.31
1.91
—
0.77
0.70
1.01
1.48
ns
Decoder
Decoder Delay (BR[9:8], BL[9:8] to DEC)
Decoder Delay (BR[7:0], BL[7:0] to DEC)
DEC98_DEL
DEC_DEL
—
2.39
2.35
—
1.85
1.82
—
1.27
1.23
—
1.02
0.99
ns