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| 型号： | OR4E041BA352-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 105/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BA352-DB |
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Lattice Semiconductor
57
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA States of Operation (continued)
Power Supply Sequencing
FPGAs are CMOS static RAM (SRAM) based program-
mable logic devices. The circuitry that the user designs
for the FPGA is implemented within the FPGA by set-
ting multiple SRAM conguration memory cells. This
unique structure as compared with typical CMOS cir-
cuits lends to having certain powerup voltage and cur-
rent requirements. This section describes these related
power issues for the ORCA Series 4 FPGAs and
FPSCs.
The exibility of Series 4 FPGAs lends itself to more
power up considerations as it mixes many power sup-
plies to meet today’s versatile system standards. The
board designer must account for the relationship of the
supplies early in board development. The proper
sequence of supplies insures that the board will not be
troubled with power up issues.
The Series 4 devices have many new design improve-
ments to prevent short-circuit contention. This conten-
tion is typically caused by conguration RAM cells in
the device not all powering up to a Q = 0 RAM state. In
order for this to occur, a minimum current was needed
to push the internal circuitry beyond the initial short-cir-
cuit-like condition to become a full CMOS circuit.
Series 4 has overcome this requirement through many
improvements which have dramatically decreased the
adverse effects of internal power up memory conten-
tion.
At power up, the internal VDD ramp and the duration of
the ramp will depend on the amount of dynamic current
available from the power supply. If a large amount of
current is available, the voltage ramp seen by the
device will be very fast. When nal voltage has been
reached, this high quiescent current is no longer
required. If the available current is limited, the time for
the device power to rise will be longer. The voltage
ramp should be monotonic with very little or no atten-
ing as the supply ramps up. It is also recommended
that the supply should not rise and fall as it is powering
up as this will cause improper power up behavior.
In Series 4 devices, it is recommended that the VDD15
supply pass through its operational threshold voltage of
approximately 1 V before the VDD33 supply reaches its
operational threshold of 2.3 V. The current required by
both VDD15 and VDD33 supplies while it passes
through their operational thresholds is approximately
between 1 and 2 amperes each. The powering of the
VDDIO supplies should be after the VDD15 and VDD33
supplies reach operational levels. This sequence and
supply currents can guarantee that the device will prop-
erly power up without any adverse effects.
In cases where the power up ramps are greater than 50
mS, it is recommended that PRGM pin be held low dur-
ing power up. However, this work around is only valid if
the power supplies meet the above mentioned current
and voltage requirements. The assertion of the PRGM
will hold off the device from conguration while the
device stabilizes and will not counter act any internal
power up requirements.
Conguration
The ORCA Series FPGA functionality is determined by
the state of internal conguration RAM. This congura-
tion RAM can be loaded in a number of different
modes. In these conguration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which conguration mode to
use is a system design issue. Conguration is dis-
cussed in detail, including the conguration data format
and the conguration modes used to load the congu-
ration data in the FPGA, following a description of the
start-up state.
Start-Up
After conguration, the FPGA enters the start-up
phase. This phase is the transition between the cong-
uration and operational states and begins when the
number of CCLKs received after INIT goes high is
equal to the value of the length count eld in the cong-
uration frame and when the end of conguration frame
has been written. The system design issue in the start-
up phase is to ensure the user I/Os become active
without inadvertently activating devices in the system
or causing bus contention. A second system design
concern is the timing of the release of global set/reset
of the PLC latches/FFs.
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E041BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E041BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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