- 您现在的位置：买卖IC网 > PDF目录189449 > OR4E041BA352-DB (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 380000 GATES, PBGA352 PDF资料下载
参数资料
| 型号： | OR4E041BA352-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 96/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BA352-DB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页当前第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页
Lattice Semiconductor
49
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Microprocessor Interface (MPI)
The Series 4 FPGAs have a dedicated synchronous
MPI function block. The MPI is programmable to oper-
ate with PowerPC/PowerQUICC MPC860/MPC8260
series microprocessors. The MPI implements an 8-,
16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to
the host processor (PowerPC) that can be used for
conguration and readback of the FPGA as well as for
user-dened data processing and general monitoring
of FPGA functions. In addition to dedicated-function
registers, the MPI bridges to the AMBA embedded sys-
tem bus through which the PowerPC bus master can
access the FPGA conguration logic, EBR and other
user logic. There is also capability to interrupt the host
processor either by a hard interrupt or by having the
host processor poll the MPI and the embedded system
bus.
The control portion of the MPI is available following
powerup of the FPGA if the mode pins specify MPI
mode, even if the FPGA is not yet congured. The
width of the data port is selectable among 8-, 16-, or
32-bit and the parity bus can be 1-, 2-, or 4-bit. In con-
guration mode the data and parity bus width are
related to the state of the M[0:3] mode pins. For post-
conguration use, the MPI must be included in the con-
guration bit stream by using an MPI library element in
your design from the ORCA macro library, or by setting
the bit of the MPI conguration control register prior to
the start of conguration. The user can also enable and
disable the parity bus through the conguration bit
stream. These pads can be used as general I/O when
they are not needed for MPI use.
Table 22 shows the interface signals that are used to
interface Series 4 devices to a PowerPC MPC860/
MPC8260 device. More information is available in the
Series 4 MPI and System Bus application note.
The ORCA FPGA is a memory-mapped peripheral to
the PowerPC processor. The MPI interfaces to the
user-programmable FPGA logic using the AMBA
embedded system bus.The MPI has access to a series
of addressable registers made accessible by the AMBA
system bus that provide MPI control and status, cong-
uration and readback data transfer, FPGA device iden-
tication, and a dedicated user scratchpad register. All
registers are 8 bits wide. The address map for these
registers and the user-logic address space utilize the
same registers as the AMBA embedded system bus.
Embedded System Bus (ESB)
Implemented using the open standard, on-chip AMBA-
AHB 2.0 specication bus, the Series 4 devices con-
nects all the FPGA elements together with a standard-
ized bus framework. The ESB facilitates
communication among MPI, conguration, EBRs, and
user logic in all the generic FPGA devices. AHB serves
the need for high-performance
system-on-chip
(SoC) as well as aligning with current synthesis design
ows. Multiple bus masters optimizes system perfor-
mance by sharing resources between different bus
masters such as the MPI and conguration logic. The
wide data bus conguration of 32-bits with 4-bit parity
supports the high-bandwidth of data-intensive applica-
tions of using the wide on-chip memory. AMBA
enhances a reusable design methodology by dening a
common backbone for IP modules.
The ESB is a synchronous bus that is driven by either
the MPI clock, internal oscillator, CCLK (slave congu-
ration modes), TCK (JTAG conguration modes), or by
a user clock from routing. In FPSCs, a clock from the
embedded block can also drive the MPI clock. During
initial conguration and reconguration the bus clock is
defaulted to the conguration clock. The post congu-
ration clock source is set during conguration. The user
has the ability to program several slaves through the
user logic interface. Embedded block RAM also inter-
faces seamlessly to the system bus.
A single bus arbiter controls the trafc on the bus by
ensuring only one master has access to the bus at any
time. The arbiter monitors a number of different
requests to use the bus and decides which request is
currently the highest priority. The conguration modes
have the highest priority and overrides all normal user
modes. Priority can be programmed between MPI and
user logic at conguration in generic FPGAs. If no pri-
ority is set a round-robin approach is used by granting
the next requesting master in a rotating xed order.
Several interfaces exist between the ESB and other
FPGA elements. The MPI interface acts as a bridge
between the external microprocessor bus and ESB.
The MPI may work in an independent clock domain
from the ESB if the ESB clock is not sourced from the
external microprocessor clock. Pipelined operation
allows high-speed memory interface to the EBR and
peripheral access without the requirement for addi-
tional cycles on the bus. Burst transfers allow optimal
use of the memory interface by giving advance infor-
mation of the nature of the transfers.
Table 23 is a listing of the ESB register le and brief
descriptions. Table 24 shows the system interrupt reg-
and command registers, all with brief descriptions.
More information is available in the Series 4 MPI and
System Bus application note.
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E041BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E041BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。