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| 型号： | OR4E041BM416-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封装： | PLASTIC, FBGA-416 |
| 文件页数： | 113/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BM416-DB |
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64
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Conguration Data Format (continued)
The number of frames, number of bits/frame, total number of bits and the required PROM size for each Series 4
device is shown in Table 32
Table 32. Conguration Frame Size
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the ORCA Series 4 FPGAs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device
for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are
agged as an ID error. This frame is automatically created by the bit stream generation program in ORCA Foundry.
Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to
1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is agged as a frame alignment
error.
Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-
uation of the checksum byte, then a checksum/parity error is agged. The checksum is the XOR of all the data
bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and
data frames.
When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will
remain in this state until either the RESET or PRGM pins are asserted The PGRM bits of the MPI control register can
also be used to reset out of the error condition and restart conguration.
If using any of the MPI modes to congure the FPGA, the specic type of bit stream error is written to one of the
MPI
registers by the FPGA conguration logic. This same information can also be read from the data register when
in asynchronous peripheral mode.
FPGA Conguration Modes
There are twelve methods for conguring the FPGA as show in Table 33. Eleven of the conguration modes are
selected on the M0, M1, M2, and M3 inputs. The twelfth conguration mode is accessed through the boundary-
scan interface. Some modes are used to select the frequency of the internal oscillator, which is the source for
CCLK in some conguration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz.
There are three basic FPGA conguration modes: master, slave, and peripheral which includes MPI mode. The
conguration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the
control signals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK
input. In the ve peripheral modes, the FPGA acts as a microprocessor peripheral. Table 33 lists the functions of
the conguration mode pins.
Devices
OR4E02
OR4E04
OR4E06
Number of Frames
1796
2436
3076
Data Bits/Frame
900
1284
1540
Maximum Conguration Data (Number of bits/frame x Number of frames)
1,616,400
3,127,824
4,737,040
Maximum PROM Size (bits) (add conguration header and postamble)
1,616,648
3,128,072
4,737,288
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E041BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E043BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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