参数资料
型号: OR4E041BM416-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA416
封装: PLASTIC, FBGA-416
文件页数: 123/151页
文件大小: 2680K
代理商: OR4E041BM416-DB
Lattice Semiconductor
73
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA Conguration Modes (continued)
5-4487(F).a
Figure 45. Slave Parallel Conguration Schematic
Daisy-Chaining
Multiple FPGAs can be congured by using a daisy-chain of the FPGAs. Daisy-chaining uses a lead FPGA and one
or more FPGAs congured in slave serial mode. The lead FPGA can be congured in any mode except slave paral-
lel mode.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on
positive CCLK and out on positive CCLK edges.
An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start indications. After
loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its
conguration data frames. The loading of conguration data continues after the lead device has received its cong-
uration data if its internal frame bit counter has not reached the length count. When the conguration RAM is full
and the number of bits received is less than the length count eld, the FPGA shifts any additional data out on
DOUT.
The conguration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the
positive edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain conguration.
The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the cong-
uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an
internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode and MPI mode
device outputs eight CCLKs for each write cycle. If the lead device is congured in slave mode, CCLK must be
routed to the lead device and to all of the daisy-chained devices.
MICRO-
PROCESSOR
OR
SYSTEM
D[7:0]
DONE
CCLK
CS1
M2
M1
M0
HDC
LDC
8
VDD
INIT
PRGM
CS0
WR
SERIES
FPGA
ORCA
M3
相关PDF资料
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OR4E041BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E042BA352-DB FPGA, 1296 CLBS, 380000 GATES, PBGA352
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OR4E042BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
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OR4E04-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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OR4E04-2BA352I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256