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参数资料
型号： OR4E041BM416-DB
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封装： PLASTIC, FBGA-416
文件页数： 87/151页
文件大小： 2680K
代理商： OR4E041BM416-DB
40
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Special Function Blocks (continued)
Start-Up Logic
The start-up logic block can be congured to coordi-
nate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of conguration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using upper-left corner routing resources.
Temperature Sensing
The built-in temperature-sensing diodes allow junction
temperature to be measured during device operation. A
physical pin (PTEMP) is dedicated for monitoring
device junction temperature. PTEMP works by forcing
a 10 A current in the forward direction, and then mea-
suring the resulting voltage. The voltage decreases
with increasing temperature at approximately
–1.69 mV/C. A typical device with a 85C device tem-
perature will measure approximately 630 mV.
Boundary-Scan
The IEEE standards 1149.1 and 1149.2 (IEEE Stan-
dard test access port and boundary-scan architecture)
are implemented in the ORCA series of FPGAs. It
allows users to efciently test the interconnection
between integrated circuits on a PCB as well as test
the integrated circuit itself. The IEEE 1149 standard is
a well-dened protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
Series 4 FPGAs are also compliant to IEEE standard
1532/D1. This standard for boundary-scan based in-
system conguration of programmable devices pro-
vides a standardized programming access and meth-
odology for FPGAs. A device, or set of devices,
implementing this standard may be programmed, read
back, erased veried, singly or concurrently, with a
standard set of resources.
The IEEE 1149 standards dene a test access port
(TAP) that consists of a four-pin interface with an
optional reset pin for boundary-scan testing of inte-
grated circuits in a system. The ORCA Series FPGA
provides four interface pins: test data in (TDI), test
mode select (TMS), test clock (TCK), and test data out
(TDO). The PRGM pin used to recongure the device
also resets the boundary-scan logic.
The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the conguration shown in
Figure 26, where boundary-scan is used to test ICs,
test data is transmitted serially into TDI of the rst
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this conguration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other congurations, mul-
tiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
Figure 26 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
5-5972(F)
Key:BSC = boundary-scan cell, BDC = bidirectional data cell, and
DCC = data control cell.
Figure 25. Printed-Circuit Board with
Boundary-Scan Circuitry
INSTRUCTION
TDO
REGISTER
BYPASS
REGISTER
TCK TMS TDI
SCAN
OUT
SCAN
IN
SCAN
OUT
SCAN
IN
SCAN
IN
SCAN
OUT
BSC
BDC
DCC
SCAN
OUT
SCAN
IN
TAPC
p_in
p_out
p_in
p_ts
p_out
p_ts
p_in
p_out
p_ts
p_out
p_ts
PL[ij]
PT[ij]
PR[ij]
PB[ij]
BDC
DCC
PLC
ARRAY
BDC
DCC
BDC
DCC
BSC
SEE ENLARGED VEIW BELOW
TMS TDI
TCK
TDO
TMS TDI
TCK
TDO
TMS TDI
TCK
TDO
TMS TDI
TCK
TDO
U1
U2
U3
U4
TDI
TCK
TDO
TMS
net a
net b
net c
S
相关PDF资料
PDF描述
OR4E041BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E042BA352-DB FPGA, 1296 CLBS, 380000 GATES, PBGA352
OR4E042BM416-DB FPGA, 1296 CLBS, 380000 GATES, PBGA416
OR4E042BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E043BA352-DB FPGA, 1296 CLBS, 380000 GATES, PBGA352
相关代理商/技术参数
参数描述
OR4E04-1BM416I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E04-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E04-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E04-2BA352C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
OR4E04-2BA352I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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