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参数资料
型号： ORSO42G5-1BMN484I
厂商： Lattice Semiconductor Corporation
文件页数： 124/153页
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
72
Toggle GSWRST_[A:B] to clear the RX FIFOs
– 30005
20
– 30105
20
– 30005
00
– 30105
00
Clear the Rejoin register bits and set Auto_Bundle
– 30A03
49
5. Eight-Link Cell Mode Initialization – ORSO82G5
This sample initialization uses 8-link cell mode. Auto_Bundle and Auto_Remove are both used for these links. The
GSWRST_[A:B] Rejoin method is used.
Set SERDES PLL to Lock to Data signal and Auto_TOH mode (per channel, all channels)
– 30804, etc. 82
Set Auto_Remove, and Rejoin
– 30A03
1B
Set 8-link cell mode
– 30A05
01
Toggle SOFT_RESET
– 30A06
01
– 30A06
00
Set the TX_CFG_DONE bit to indicate the transmitter is completely congured
– 30A07
01
Toggle GSWRST_[A:B] to clear the Rx FIFOs
– 30005
20
– 30105
20
– 30005
00
– 30105
00
Once all of the RX_LINK_GOODs are high, Clear the Rejoin register bits and set Auto_Bundle
– 30A03
49
Reset Conditions
The SERDES block can be reset in one of three different ways: on power up, using the hardware reset
(PASB_RESETN) or by setting bits in the control registers. The power up reset process begins when the power
supply voltage ramps up to approximately 80% of the nominal value of 1.5V. Following this event, the device will be
ready for normal operation after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES blocks and resets all core control, status and data path registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST bit to a logic 1 in the
SERDES channel conguration register. The device will be ready 3 ms after the SWRST bit is deasserted. Simi-
larly, all four channels per block SERDES can be reset by setting the global reset bit GSWRST. The device will be
ready for normal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset options resets
only the SERDES internal registers and counters on a per channel or per block basis. The core non-SERES regis-
ters and logic blocks are not affected. It should also be noted that the embedded core registers and logic blocks
cannot be accessed until after FPGA conguration is complete.
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相关代理商/技术参数
参数描述
ORSO42G5-2BM484C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BM484I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BMN484C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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