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| 型号： | P0528 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 26/56页 |
| 文件大小： | 0K |
| 描述： | BOARD DEV DE1 ALTERA |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone II 2C20 |
| 所含物品： | DE1 板，电源，USB 线缆，塑料盖和软件 |
| 配用： | P0033-ND - BOARD ADAPTER HSMC TO GPIO P0006-ND - BOARD ADAPTER THDB-SUM P0001-ND - MODULE DIGITAL CAMERA 5MP (D5M) P0307-ND - KIT DEV 4.3" LCD TOUCH PANEL |
| 相关产品： | 544-2107-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2106-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2105-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2104-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2103-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2102-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2101-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1781-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-1670-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1669-ND - IC CYCLONE II FPGA 20K 484-FBGA 更多... |
| 其它名称： | DE1 |
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DE1 User Manual
Chapter 4
Using the DE1 Board
This chapter gives instructions for using the DE1 board and describes each of its I/O devices.
4.1 Configuring the Cyclone II FPGA
The procedure for downloading a circuit from a host computer to the DE1 board is described in the
tutorial Quartus II Introduction . This tutorial is found in the DE1_tutorials folder on the DE1
System CD-ROM, and it is also available on the Altera DE1 web pages. The user is encouraged to
read the tutorial first, and to treat the information below as a short reference.
The DE1 board contains a serial EEPROM chip that stores configuration data for the Cyclone II
FPGA. This configuration data is automatically loaded from the EEPROM chip into the FPGA each
time power is applied to the board. Using the Quartus II software, it is possible to reprogram the
FPGA at any time, and it is also possible to change the non-volatile data that is stored in the serial
EEPROM chip. Both types of programming methods are described below.
1. JTAG programming: In this method of programming, named after the IEEE standards Joint
Test Action Group , the configuration bit stream is downloaded directly into the Cyclone II
FPGA. The FPGA will retain this configuration as long as power is applied to the board;
the configuration is lost when the power is turned off.
2. AS programming: In this method, called Active Serial programming, the configuration bit
stream is downloaded into the Altera EPCS4 serial EEPROM chip. It provides non-volatile
storage of the bit stream, so that the information is retained even when the power supply to
the DE1 board is turned off. When the board's power is turned on, the configuration data in
the EPCS4 device is automatically loaded into the Cyclone II FPGA.
The sections below describe the steps used to perform both JTAG and AS programming. For both
methods the DE1 board is connected to a host computer via a USB cable. Using this connection, the
board will be identified by the host computer as an Altera USB Blaster device. The process for
installing on the host computer the necessary software device driver that communicates with the
USB Blaster is described in the tutorial Getting Started with Altera's DE1 Board . This tutorial is
available on the DE1 System CD-ROM and from the Altera DE1 web pages.
Configuring the FPGA in JTAG Mode
24
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