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| 型号： | P0528 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 38/56页 |
| 文件大小： | 0K |
| 描述： | BOARD DEV DE1 ALTERA |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone II 2C20 |
| 所含物品： | DE1 板，电源，USB 线缆，塑料盖和软件 |
| 配用： | P0033-ND - BOARD ADAPTER HSMC TO GPIO P0006-ND - BOARD ADAPTER THDB-SUM P0001-ND - MODULE DIGITAL CAMERA 5MP (D5M) P0307-ND - KIT DEV 4.3" LCD TOUCH PANEL |
| 相关产品： | 544-2107-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2106-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2105-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2104-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2103-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2102-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2101-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1781-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-1670-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1669-ND - IC CYCLONE II FPGA 20K 484-FBGA 更多... |
| 其它名称： | DE1 |
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DE1 User Manual
4.6 Using VGA
The DE1 board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization
signals are provided directly from the Cyclone II FPGA, and a 4-bit DAC using resistor network is
used to produce the analog data signals (red, green, and blue). The associated schematic is given in
Figure 4.11 and can support standard VGA resolution (640x480 pixels, at 25 MHz).
Figure 4.11. VGA circuit schematic.
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational web sites (for example, search for “VGA signal timing”). Figure 4.12 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time a in the figure) is applied to the horizontal
synchronization ( hsync ) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period
called the back porch ( b ) after the hsync pulse occurs, which is followed by the display interval ( c ).
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