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| 型号： | P0528 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 39/56页 |
| 文件大小： | 0K |
| 描述： | BOARD DEV DE1 ALTERA |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone II 2C20 |
| 所含物品： | DE1 板，电源，USB 线缆，塑料盖和软件 |
| 配用： | P0033-ND - BOARD ADAPTER HSMC TO GPIO P0006-ND - BOARD ADAPTER THDB-SUM P0001-ND - MODULE DIGITAL CAMERA 5MP (D5M) P0307-ND - KIT DEV 4.3" LCD TOUCH PANEL |
| 相关产品： | 544-2107-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2106-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2105-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2104-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2103-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2102-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2101-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1781-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-1670-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1669-ND - IC CYCLONE II FPGA 20K 484-FBGA 更多... |
| 其它名称： | DE1 |
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DE1 User Manual
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch ( d ) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization ( vsync )
is the same as shown in Figure 4.12, except that a vsync pulse signifies the end of one frame and the
start of the next, and the data refers to the set of rows in the frame (horizontal timing). Figures 4.13
and 4.14 show, for different resolutions, the durations of time periods a , b , c , and d for both
horizontal and vertical timing.
The pin assignments between the Cyclone II FPGA and the VGA connector are listed in Table 4.8.
An example of code that drives a VGA display is described in Sections 5.2 and 5.3.
Figure 4.12. VGA horizontal timing specification.
VGA mode
Horizontal Timing Spec
Configuration
Resolution(HxV)
a(us)
b(us)
c(us)
d(us)
Pixel clock(Mhz)
VGA(60Hz)
640x480
3.8
1.9
25.4
0.6
25
(640/c)
Figure 4.13. VGA horizontal timing specification.
VGA mode
Vertical Timing Spec
Configuration
Resolution
(HxV)
a(lines)
b(lines)
c(lines)
d(lines)
VGA(60Hz)
640x480
2
33
480
10
Figure 4.14. VGA vertical timing specification.
Signal Name
VGA_R[0]
VGA_R[1]
VGA_R[2]
VGA_R[3]
VGA_G[0]
VGA_G[1]
VGA_G[2]
VGA_G[3]
FPGA Pin No.
PIN_D9
PIN_C9
PIN_A7
PIN_B7
PIN_B8
PIN_C10
PIN_B9
PIN_A8
37
Description
VGA Red[0]
VGA Red[1]
VGA Red[2]
VGA Red[3]
VGA Green[0]
VGA Green[1]
VGA Green[2]
VGA Green[3]
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