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| 型号： | P0528 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 54/56页 |
| 文件大小： | 0K |
| 描述： | BOARD DEV DE1 ALTERA |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone II 2C20 |
| 所含物品： | DE1 板，电源，USB 线缆，塑料盖和软件 |
| 配用： | P0033-ND - BOARD ADAPTER HSMC TO GPIO P0006-ND - BOARD ADAPTER THDB-SUM P0001-ND - MODULE DIGITAL CAMERA 5MP (D5M) P0307-ND - KIT DEV 4.3" LCD TOUCH PANEL |
| 相关产品： | 544-2107-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2106-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2105-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2104-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2103-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2102-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2101-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1781-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-1670-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1669-ND - IC CYCLONE II FPGA 20K 484-FBGA 更多... |
| 其它名称： | DE1 |
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DE1 User Manual
5.4 SD Card Music Player
Many commercial media/audio players use a large external storage device, such as an SD card or
CF card, to store music or video files. Such players may also include high-quality DAC devices so
that good audio quality is produced. The DE1 board provides the hardware and software needed for
SD card access and professional audio performance so that it is possible to design advanced
multimedia products using the DE1 board.
In this demonstration we show how to implement an SD Card Music Player on the DE1 board, in
which the music files are stored in an SD card and the board can play the music files via its
CD-quality audio DAC circuits. We use the Nios II processor to read the music data stored in the
SD Card and use the Wolfson WM8731 audio CODEC to play the music.
The audio CODEC is configured in the slave mode, where external circuitry must provide the
ADC/DAC serial bit clock ( BCK ) and left/right channel clock ( LRCK ) to the audio CODEC. As
shown in Figure 5.11, we provide an Audio DAC Controller to achieve the clock generation and the
data flow control. The Audio DAC Controller is integrated into the Avalon bus architecture, so that
the Nios II processor can control the application.
During operation the Nios II processor will check if the FIFO memory of the Audio DAC Controller
becomes full. If the FIFO is not full, the processor will read a 512-byte sector and send the data to
the FIFO of the Audio DAC Controller via the Avalon bus. The Audio DAC Controller uses a 48
kHz sample rate to send the data and clock signals to the audio CODEC. The design also mixes the
data from microphone-in with line-in for the Karaoke-style effects.
Figure 5.11. Block diagram of the SD music player demonstration.
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