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| 型号： | P87C380 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 14/84页 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
14
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
7.3.3
ADC C
ONTROL
R
EGISTER
(ADCDAT)
Table 9
ADC Control Register (SFR address C1H)
Table 10
Description of ADCDAT bits
7.3.4
14-
BIT
PWM
DATA LATCHES
(PWM10H
AND
PWM10L)
Table 11
PWM High-byte Data Latch (PWM10H; SFR address C6H)
Table 12
Description of PWM10H bits
2
ADCE
ADC channel enable
. This flag enables the ADC function and also switches the pins
ADC0/P3.2 and ADC1/P3.3 to the ADC inputs function. If ADCE = 1, the ADC function
is enabled and the pin functions are ADC0 and ADC1 respectively. If ADCE = 0, the
ADC function is disabled and the pin functions are I/O ports P3.2 and P3.3 respectively.
Polarity selection bit for the PWM10 output (14-bit PWM)
. If P14LVL = 1, PWM10
output is inverted. If P14LVL = 0, PWM10 output is not inverted.
Polarity selection bit for the PWM0 to PMM9 outputs (8-bit PWM)
. If P8LVL = 1,
PWM0 to PWM9 outputs are inverted. If P8LVL = 0, PWM0 to PWM9 outputs are not
inverted.
1
P14LVL
0
P8LVL
7
6
5
4
3
2
1
0
DACHL
DAC3
DAC2
DAC1
DAC0
COMP
BIT
SYMBOL
DACHL
DESCRIPTION
7 to 6
5
Reserved.
ADC input channels selection
. If DACHL = 1, then input channel
ADC1 is selected. If DACHL = 0, then input channel ADC0 is selected.
Reference voltage level selection
. The 4 bits select the analog output
voltage (V
ref
) of the 8-bit DAC. For V
ref
values see Table 31.
Comparison result; read only
. If COMP = 1, then the ADC input
voltage is higher than the reference voltage. If COMP = 0, then the ADC
input voltage is lower than the reference voltage.
4 to 1
DAC3 to DAC0
0
COMP
7
6
5
4
3
2
1
0
EW1
PWM10H.6
PWM10H.5
PWM10H.4
PWM10H.3
PWM10H.2
PWM10H.1
PWM10H.0
BIT
SYMBOL
DESCRIPTION
7
EW1
Watchdog Timer enable flag
. This flag is associated with the flag EW2
(SFR DFCON) and EW0 (SFR PWM10L) to form the enable/disable
control key for the Watchdog Timer; see Tables 8 and 14.
7 upper data bits for the 14-bit PWM.
6 to 0
PWM10H.6 to PWM10H.0
BIT
SYMBOL
DESCRIPTION
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