参数资料
型号: P87C380
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
中文描述: 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42
封装: 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件页数: 61/84页
文件大小: 420K
代理商: P87C380
1997 Dec 12
61
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
19.2.6
V
ERTICAL MODE DETECTION
To detect the vertical mode parameters Vper, Vpol and
Vpres, a circuit can be used which is almost similar to that
for the horizontal mode detection. The only difference is
that now the period time of one frame (instead of 4 lines)
is measured. The presence indication for the vertical sync
also contains a hysteresis of about 1.2%.
The formula to calculate the hysteresis is also similar to the
condition of HSYNC processing. A 12-bit counter is used
to count the clock number during one frame. Again FF0H
(4080 decimal) and FC0H (4032 decimal) are taken as the
threshold for Vfreq1 and Vfreq2 respectively, but the clock
FOSV = FOSH/76. Vfreq1, Vfreq2 and Hysteresis are
calculated as follows:
Counter value
(
Counter value
(
f
V
Vfreq1
)
--------------FOSV
76
×
76
×
4080
---FOSH
=
=
=
f
V
Vfreq2
)
--------------FOSV
4032
---FOSH
=
=
=
The hysteresis result,
Hysteresis
,
is shown in Table 64.
If the new VSYNC frequency is larger than the previous
VSYNC frequency, the time from mode change to interrupt
issued is approximately from
((Vperiod
(new)
×
2) + Vperiod
(previous)
) to (Vperiod
(new)
×
3).
If the new VSYNC frequency is not in the static state and
is smaller than the previous VSYNC frequency, the time
from mode change to interrupt issued is approximately
from Vperiod
(new)
to Vperiod
(new)
×
2. If the new VSYNC
frequency is in the static state, the time from mode change
to interrupt issued is approximately from
(4080
×
6.3 us)
Vperiod
(previous)
to 4080
×
6.3
μ
s.
Vfreq1
Hfreq2
(
)
Hfreq1
=
Table 65
Hysteresis in the Vpres detection
(f
clk
)
(MHz)
FOSH
(MHz)
Vfreq1
(MHz)
Vfreq2
(MHz)
HYSTERESIS
(%)
10
12
16
10
12
8
32.25
38.70
25.80
32.63
39.16
26.11
1.2
1.2
1.2
The polarity can be measured by looking to the level of the
input sync at
1
4
of the frame time. The mode change in
vertical the frame period will be detected if there is a
change for a longer time than 3 frame periods.
The accuracy of Vper can calculated by the following
formula:
The hysteresis results and the accuracy of Vper are shown
in Table 63.
19.2.7
H
ORIZONTAL PULSE GENERATOR
Through the control flags, HPG1 and HPG0, the horizontal
pulse generator is able to generate the HSYNC
out
signal
with the following formats:
1.
The same pulse as the input horizontal sync, or a
substitution pulse (with a fixed length) in case of a
missing sync pulse.
Accuracy in V
(vertical counter value)
100%
76
×
×
FOSH
(
)
-----------------------100%
100%
FOSV
(
f
V
)
-------------------------
f
V
--------------------------------------
=
=
=
2.
A pulse starting at the beginning of the input horizontal
sync but now with a fixed length, or a substitution pulse
(with fixed length).
A free running sync pulse.
The same pulse as the input horizontal sync. The
substitution pulse is inhibited even if HSYNC is
missing.
3.
4.
To be able to generate a substitution pulse the down
counter, depicted in Fig.23, is loaded at each incoming
sync with a period time just a bit longer than the measured
Hper. If now normal syncs are present then the counter will
be loaded just before it reaches 000H. Therefore the
counter will not generate a pulse (in Fig.23, HPST remains
LOW). However, if a sync pulse is missing the counter will
reach 000H and generates a substitution pulse, HPST. At
the same time it will load itself again for the next run. To
generate free running pulses the only thing to do is to load
the down counter with the parameter HFP and to stop the
load pulses coming from the input sync, HSYNC_P. So,
the signal HPST is either a free running pulse or a pulse in
case an input sync is missing.
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