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| 型号： | P87C380 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 66/84页 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
66
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
20 POWER MANAGEMENT
The P83C880 supports power management. The
hardware mode detection complies to the Device Power
Management Signalling (DPMS) according to the
specification of VESA. The microcontroller is able to
distinguish between ‘Normal’, ‘Standby’, ‘Suspend’ and
‘Power off’ mode by detecting the frequency of HSYNC
and VSYNC. HSYNC is an active signal if its frequency is
above 15 kHz; otherwise, it is inactive. For VSYNC 40 Hz
is the threshold to judge if it is active or inactive. See also
Section 19.3.1. The exact values for the threshold depend
on the chosen crystal oscillator frequency:
10, 12 or 16 MHz.
The information about the status of HSYNC and VSYNC
can be represented by the bits, Hpres and Vpres in SFR
MDCST (address F8H).
The combination of Hpres and Vpres in relation to the
operating mode is shown in Table 66.
In the case of DDC2AB protocol, apart from hardware
mode detection, the protocol of ACCESS.bus also
supports Device Power Management Signalling (DPMS)
commands. In some operating modes the microcontroller
might enter a kind of power saving mode, i.e. Idle or
Power-down mode. In this situation the extremely low
retention voltage of 1.8 V for internal memory can support
the microcontroller to save its state before switching to Idle
or Power-down mode.
One set of I/O ports with the capability to drive LEDs can
help to highlight the current operating mode of monitors. It
is also possible to control the power consumption sources
like heater, main supply etc., through an I/O port in a
related operating mode.
Table 66
Display Power Management modes
OPERATING MODES
HSYNC
Hpres
VSYNC
Vpres
Normal
Standby
Suspend
Power off
active
inactive
active
inactive
1
0
1
0
active
active
inactive
inactive
1
1
0
0
21 CONTROL MODES
The microcontroller can operate in different control modes
(e.g. for emulation or OTP programming) by means of a
10-bit serial code that is shifted into the RESET input. The
signal at the XTAL1 pin serves as the shift clock.
The code is built up as follows: 0 XXXXX 0101; whereby
the first ‘0’ is the start bit, followed by a 5-bit code and
completed by ‘0101’. The 5-bit code determines the mode.
Normal mode is reached when no code is shifted in, but
the RESET pin remains HIGH for at least 10 cycles of the
XTAL1 input plus 20
μ
s.
When an OTP Programming/Verification, Emulation or a
Test mode should be entered, the timing must be as
shown in Fig.34.
The RESET signal is sampled on the rising edge of
XTAL1. Set-up and hold times for the RESET signal with
respect to the XTAL1 rising edge are 10 ns each.
The procedure to enter a specific control mode is as
follows:
1.
Reset the microcontroller (CPU) by keeping the
RESET signal HIGH for at least 10 XTAL1 clock cycles
to escape any other control mode, plus at least 20
μ
s
(minimum of 24 internal clock cycles) to reset the
internal logic.
2.
Shift in the specific code for the required control mode
(e.g. 0110000101 for Emulation mode) via the
RESET pin and the XTAL1 clock (MSB first).
3.
After the 10th bit the RESET signal should go LOW
within 9 cycles of XTAL1, otherwise the
microcontroller will enter Normal mode.
For the OTP Programming/Verification control modes see
Chapter 22.
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