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| 型号： | P87C380 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 28/84页 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
28
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
Fig.11 On-chip reset configuration.
handbook, full pagewidth
MGG022
SCHMITT
TRIGGER
RESET
CIRCUITRY
RRESET
overflow timer T2
Power-on-reset
RSTOUT
8 k
10
μ
F
VDD
on-chip circuit
RESET
POC
13.1
External reset
Pin RESET is connected to a Schmitt trigger for noise
reduction (see Fig.11). A reset is accomplished by holding
the RESET pin HIGH for at least 16 machine cycles (192
system clocks) while the oscillator is running.
An automatic reset can be obtained by switching on V
DD
,
if the RESET pin is connected to V
DD
via a capacitor and
a resistor as illustrated in Fig.11. The V
DD
rise time must
not exceed 10 ms and the capacitor should be at least
10
μ
F. The decrease of the RESET pin voltage depends
on the capacitor and the external resistor R
RESET
. The
voltage must remain above the lower threshold for at least
the oscillator start-up time plus 2 machine cycles.
13.2
Power-on-reset
An on-chip Power-on-reset circuit that detects the supply
voltage rise or fall and accordingly generates a power-on
reset pulse (see Fig.12).
In the case of supply voltage rise, the power-on reset
signal will follow the supply voltage rise; after reaching the
trip level V
t
the power-on reset signal will maintain the
same behaviour, and returns to a LOW state after a time
interval T
p
.
In the case of supply voltage fall, after the trip level V
t
is
reached, the power-on reset signal will follow the
waveform of the supply voltage for time interval T
p
.
The time interval T
p
guarantees that a complete power-on
reset pulse can trigger the internal reset signal. However,
to ensure that the oscillator is stable before the controller
starts, the clock signals are gated away from the CPU for
a further 2048 oscillator cycles.
The values of V
t
, T
p
and a process tolerance of
±
V
t
can
be found in Chapter 25; currently V
t
= 3.9 V, T
p
= 10
μ
s
and
V
t
= 0.3 V.
13.3
T2 (Watchdog Timer Data Register) overflow
The length of the output pulse from T2 is 3 machine cycles.
A pulse of such short duration is necessary in order to
recover from a processor or system fault as fast as
possible.
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