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| 型号： | P87C380 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 42/84页 |
| 文件大小： | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
42
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
Table 37
Description of DDCCON bits
Note
1.
These bits are R/W.
BIT
SYMBOL
EX_DAT
DESCRIPTION
7
6
Reserved.
This bit defines the size of the EDID data. It is related to the function of the post
increment of the address pointer, DDCADR. When the upper limit is reached, the
address pointer will wrap around to 00H. If EX_DAT = 1, the data size is 256 bytes.
If EX_DAT = 0, the data size is 128 bytes; the addressing range for the EDID data
buffer is mapped from 0 to 127, the rest (128 to 255) can still be used by the system.
This bit indicates if the software/CPU is needed to take care of the operation of DDC1
protocol. If SWENB = 1, in DDC1 protocol, the CPU is interrupted during the period of
the 9th transmitting bit so that the software service routine can update the hold
register of the transmitter by moving new data from the appropriate area (it is not
necessary to be the RAM buffer). This transferring must be done within 40
μ
s.
If SWENB = 0, the hold register of the transmitter will be automatically updated from
the RAM buffer without the intervention of the CPU.
Reserved.
Interrupt request bit (002BH is assigned as the interrupt vector address). This bit is only
valid in DDC1 protocol while software handling is enabled (SWENB = 1). This bit is set
by hardware and should be cleared by software in an interrupt service routine. If DDC1
is fully under the hardware control (SWENB = 0), this bit can be ignored.
If DDC1_int = 1, interrupt request is pending. If DDC1_int = 0, there are no interrupt
request.
DDC1enable
(1)
DDC1 enable control bit. If DDC1enable = 1, DDC1 is enabled. If DDC1enable = 0,
DDC1 is disabled (the activity on VCLK is ignored).
SWH_int
(1)
Interrupt request bit (002BH is assigned as the interrupt vector address). This bit is
used to indicate that DDC interface switches from DDC1 to DDC2 (i.e. the
HIGH-to-LOW transition is observed on pin SCL1). This bit should be cleared by
software in an interrupt service routine. If SWH_int = 1, interrupt request is pending.
If SWH_int = 0, there is no interrupt request.
M0
(1)
DDC mode indication bit. If M0 = 0, DDC1 is set; if M0 = 1, DDC2 is set.
5
SWENB
4
3
DDC1_int
(1)
2
1
0
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