参数资料
型号: P89LPC925FDH
厂商: NXP Semiconductors N.V.
元件分类: 8位微控制器
英文描述: 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB-8 kB 3 V low-power Flash with 8-bit A-D converter
封装: P89LPC924FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1<Always Pb-free,;P89LPC925FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html&
文件页数: 20/49页
文件大小: 233K
代理商: P89LPC925FDH
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
27 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark: During a power cycle, VDD must fall below VPOR (see Table 8 “DC electrical
characteristics” on page 40) before power is reapplied, in order to ensure a power-on
reset.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user congured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz);
Power-on detect;
Brownout detect;
Watchdog Timer;
Software reset;
UART break character detect reset.
For every reset source, there is a ag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These ag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one ag bit
may be set:
During a power-on reset, both POF and BOF are set but the other ag bits are
cleared.
For any other reset, previously set ag bits that have not been cleared will remain
set.
8.16.1
Reset vector
Following reset, the P89LPC924/925 will fetch instructions from either address 0000h
or the Boot address. The Boot address is formed by using the Boot Vector as the high
byte of the address and the low byte of the address = 00h.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on
(see
P89LPC924/925 User’s Manual). Otherwise, instructions will be fetched from
address 0000H.
8.17 Timers/counters 0 and 1
The P89LPC924/925 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be congured to
operate either as timers or event counter. An option to automatically toggle the T0
and/or T1 pins upon timer overow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition
at its corresponding external input pin, T0 or T1. In this function, the external input is
sampled once during every machine cycle.
Timer 0 and Timer 1 have ve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1,
2 and 6 are the same for both Timers/Counters. Mode 3 is different.
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