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| 型号： | P89LPC925FDH |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 8位微控制器 |
| 英文描述： | 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB-8 kB 3 V low-power Flash with 8-bit A-D converter |
| 封装： | P89LPC924FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1<Always Pb-free,;P89LPC925FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html& |
| 文件页数： | 31/49页 |
| 文件大小： | 233K |
| 代理商： | P89LPC925FDH |
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Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
37 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Flash programming and erasing: There are four methods of erasing or
programming of the Flash memory that may be used. First, the Flash may be
programmed or erased in the end-user application by calling low-level routines
through a common entry point. Second, the on-chip ISP boot loader may be invoked.
This ISP boot loader will, in turn, call low-level routines through the same common
entry point that can be used by the end-user application. Third, the Flash may be
programmed or erased using the parallel method by using a commercially available
EPROM programmer which supports this device. Fourth, the Flash may be
programmed or erased using a commercially available EPROM programmer which
supports the ICP protocol. This device does not provide for direct verication of code
memory contents. Instead this device provides a 32-bit CRC result on either a sector
or the entire 4 kB/8 kB of user code space.
Boot ROM: When the microcontroller programs its own Flash memory, all of the
low-level details are handled by code that is contained in a Boot ROM that is separate
from the Flash memory. A user program simply calls the common entry point in the
Boot ROM with appropriate parameters to accomplish the desired operation. The
Boot ROM include operations such as erase sector, erase page, program page, CRC,
program security bit, etc. The Boot ROM occupies the program memory space at the
top of the address space from FF00 to FFFF hex, thereby not conicting with the user
program memory space.
Power-on reset code execution: The P89LPC924/925 contains two special Flash
elements: the Boot Vector and the Boot Status Bit. Following reset, the
P89LPC924/925 examines the contents of the Boot Status Bit. If the Boot Status Bit
is set to zero, power-up execution starts at location 0000H, which is the normal start
address of the user’s application code. When the Boot Status Bit is set to a one, the
contents of the Boot Vector is used as the high byte of the execution address and the
low byte is set to 00H. The factory default setting is 1FH for the P89LPC925 and
corresponds to the address 1F00H for the default ISP boot loader. The factory default
setting is 0FH for the P89LPC924 and corresponds to the address 0F00H for the
default ISP boot loader. This boot loader is pre-programmed at the factory into this
address space and can be erased by the user. Users who wish to use this loader
should take precautions to avoid erasing the 1 kB sector from 1C00H to 1FFFH
in the P89LPC925 or the 1 kB sector from 0C00H to 0FFFH in the P89LPC924.
Instead, the page erase function can be used to erase the eight 64-byte pages
which comprise the lower 512 bytes of the sector. A custom boot loader can be
written with the Boot Vector set to the custom boot loader, if desired.
Hardware activation of the boot loader: The boot loader can also be executed by
forcing the device into ISP mode during a power-on sequence (see the
P89LPC924/925 User’s Manual for specic information). This has the same effect as
having a non-zero Boot Status Bit. This allows an application to be built that will
normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector is changed, it will no longer point to the
factory pre-programmed ISP boot loader code. If this happens, the only way it is
possible to change the contents of the Boot Vector is through the parallel or ICP
programming methods, provided that the end user application does not contain a
customized loader that provides for erasing and reprogramming of the Boot Vector
and Boot Status Bit. After programming the Flash, the Boot Status Bit should be
programmed to zero in order to allow execution of the user’s application code
beginning at address 0000H.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC925FDH,529 | 功能描述:8位微控制器 -MCU 80C51 8K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC925FDH-S | 制造商:NXP Semiconductors 功能描述:MCU 8-bit P89 80C51 CISC 8KB Flash 2.5V/3.3V 20-Pin TSSOP |
| P89LPC925FN,129 | 功能描述:8位微控制器 -MCU 8K FL/256B RAM/I2C/UART/ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC925FN-S | 功能描述:8位微控制器 -MCU 80C51 8K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC92X1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC |
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