参数资料
型号: P89LPC925FDH
厂商: NXP Semiconductors N.V.
元件分类: 8位微控制器
英文描述: 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB-8 kB 3 V low-power Flash with 8-bit A-D converter
封装: P89LPC924FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1<Always Pb-free,;P89LPC925FDH<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html&
文件页数: 47/49页
文件大小: 233K
代理商: P89LPC925FDH
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data
Rev. 03 — 15 December 2004
7 of 49
9397 750 14471
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P1.0 - P1.7
12, 11, 10,
9, 8, 4, 3,
2
I/O, I [1] Port 1: Port 1 is an 8-bit I/O port with a user-congurable output type, except for three
pins as noted below. During reset Port 1 latches are congured in the input only mode
with the internal pull-up disabled. The operation of the congurable Port 1 pins as inputs
and outputs depends upon the port conguration selected. Each of the congurable
port pins are programmed independently. Refer to Section 8.13.1 “Port congurations”
and Table 8 “DC electrical characteristics” for details. P1.2 - P1.3 are open drain when
used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
12
I/O
P1.0 — Port 1 bit 0.
O
TXD — Transmitter output for the serial port.
11
I/O
P1.1 — Port 1 bit 1.
I
RXD — Receiver input for the serial port.
10
I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter 0 external count input or overow output (open-drain when used as
output).
I/O
SCL — I2C serial clock input/output.
9
I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C serial data input/output.
8
I/O
P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
4I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input (if selected via FLASH conguration). A LOW on this pin
resets the microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specied level. When system power is removed VDD will fall below the
minimum specied operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit may be
required to hold the device in reset when VDD falls below the minimum specied
operating voltage.
3
I/O
P1.6 — Port 1 bit 6.
2
I/O
P1.7 — Port 1 bit 7.
Table 3:
Pin description…continued
Symbol
Pin
Type
Description
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