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参数资料
| 型号： | PALLV22V10-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| 中文描述： | EE PLD, 15 ns, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 15/19页 |
| 文件大小： | 380K |
| 代理商： | PALLV22V10-15JC |
PALLV22V10 and PALLV22V10Z Families
5
USE
GAL
DEVICES
FOR
NEW
DESIGNS
Note that preset and reset control the ip-op, not the output pin. The output level is determined
by the output polarity selected.
Benets of Lower Operating Voltage
The PALLV22V10 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower
operating power consumption, longer battery life, and/or smaller batteries for notebook
applications.
Because power is proportional to the square of the voltage, reduction of the supply voltage from
5.0 V to 3.3 V signicantly reduces power consumption. This directly translates to longer battery
life for portable applications. Lower power consumption can also be used to reduce the size and
weight of the battery. Thus, 3.3 V designs facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise
generation and provides a less hostile environment for board design. A lower operating voltage
also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
3.3-V (CMOS) and 5-V (CMOS and TTL) Compatible Inputs and I/O
Input voltages can be at TTL levels. Additionally, the PALLV22V10 can be driven with true 5-V
CMOS levels due to special input and I/O buffer circuitry.
Power-Up Reset
All ip-ops power up to a logic LOW for predictable system initialization. Outputs of the
PALLV22V10 will depend on the programmed output polarity. The VCC rise must be monotonic,
and the reset delay time is 1000ns maximum.
Register Preload
The registers on the PALLV22V10 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be veried by loading illegal states and observing
proper recovery.
Security Bit
After programming and verication, a PALLV22V10 design can be secured by programming the
security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern
by a device programmer, securing proprietary designs from competitors. When the security bit is
programmed, the array will read as if every bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of the entire pattern.
Programming and Erasing
The PALLV22V10 can be programmed on standard logic programmers. It also may be erased to
reset a previously congured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.
相关PDF资料 |
PDF描述 |
|---|---|
| PALLV22V10-15JI | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10-15PC | Header Connector,PCB Mnt,RECEPT,5 Contacts,PIN,0.1 Pitch,PC TAIL Terminal,LOCKING MECH |
| PALLV22V10-7JC | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PLSI1032E-70LJ | High-Density Programmable Logic |
| PLSI1032E-80LJ | High-Density Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PALLV22V10-15JI | 制造商:Lattice Semiconductor Corporation 功能描述: |
| PALLV22V10-15PC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10-7JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25PI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
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