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参数资料
| 型号： | PALLV22V10-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| 中文描述： | EE PLD, 15 ns, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 16/19页 |
| 文件大小： | 380K |
| 代理商： | PALLV22V10-15JC |
6
PALLV22V10 and PALLV22V10Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
Quality and Testability
The PALLV22V10 offers a very high level of built-in quality. The erasability of the CMOS
PALLV22V10 allows direct testing of the device array to guarantee 100% programming and
functional yields.
Technology
The high-speed PALLV22V10 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are designed
to be 3.3-V and 5-V device compatible. This technology provides strong input-clamp diodes,
output slew-rate control, and a grounded substrate for clean switching.
Zero-Standby Power Mode
The PALLV22V10Z features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 30 ns), the PALLV22V10Z will go into standby mode, shutting down
most of its internal circuitry. The current will go to almost zero (ICC <30 A). The outputs will
maintain the states held before the device went into the standby mode.
If a macrocell is used in registered mode, switching pin CLK/I0 will not affect standby mode status
for that macrocell. If a macrocell is used in combinatorial mode, switching pin CLK/I0 will affect
standby mode status for that macrocell.
This feature reduces dynamic ICC proportionally to the number of registered macrocells used. If all
macrocells are used as registers and only CLK/I0 is switching, the device will not be in standby
mode, but dynamic ICC will typically be <2 mA. This is because only the CLK/I0 buffer will draw
current. The use of combinatorial macrocells will add on average 5 mA per macrocell (at 25 MHz)
under these same conditions.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies.
Product-Term Disable
On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut
off from these product terms so that they do not draw current. Product-term disabling results in
considerable power savings. This saving is greater at the higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.
相关PDF资料 |
PDF描述 |
|---|---|
| PALLV22V10-15JI | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10-15PC | Header Connector,PCB Mnt,RECEPT,5 Contacts,PIN,0.1 Pitch,PC TAIL Terminal,LOCKING MECH |
| PALLV22V10-7JC | Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PLSI1032E-70LJ | High-Density Programmable Logic |
| PLSI1032E-80LJ | High-Density Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PALLV22V10-15JI | 制造商:Lattice Semiconductor Corporation 功能描述: |
| PALLV22V10-15PC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
| PALLV22V10-7JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PALLV22V10Z-25PI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device |
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