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| 型号： | PCM9211PTR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, TOKEN RING TRANSCEIVER, PQFP48 |
| 封装： | GREEN, PLASTIC, LQFP-48 |
| 文件页数： | 35/121页 |
| 文件大小： | 1219K |
| 代理商： | PCM9211PTR |
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SBAS495 – JUNE 2010
www.ti.com
ADC: Clock Source Configuration
A number of clock sources for the ADC are provided. Clock source selection is done using the ADCLK[2:0]
register (Register 42h). In most applications, the onboard clock (XTI) is used, but using another clock source
(such as a DIR recovered clock or AUXIN clock) is also possible. The ADC can only be used in a slave mode
unless it is set to run in standalone mode.
1. Driving the ADC From an XTI (External) Clock
The dividing ratio for the incoming clock (XTI) is set by using the registers XSCK[1:0], XBCL[1:0], and
XLRCL[1:0] (Register 31h). These registers provide the ability to drive the device up to 192 kHz; however,
the integrated ADC sample rate is only supported in the range of 16 kHz to 96 kHz.
Keep this limitation in mind when setting the registers.
2. Driving the ADC From the DIR Clock
The ADC maximum specified sampling frequency is 96 kHz. The maximum supported frequency of the DIR
is 216 kHz. Therefore, special care must be taken when driving the ADC clock from the DIR receiver clock.
Driving the ADC clock from the DIR is done by setting Register 42h/ADCLK-001. An ADC clock limiter is set
in Register 42h/ADFSLMT. This limiter only functions when the DIR is selected as the clock source.
If the DIR receives data that are over 96 kHz and generates a clock for the ADC that exceeds its
specifications, then the ADC is forced into a power-down state. If the limiter is not set, the ADC will run
beyond its specified limits and generate erroneous data.
ADC: Standalone Operation
This configuration allows separate use of the ADC from the rest of the device. In this configuration, PCM data
(SCK, BCK, LRCK, and Data) are routed directly out to MPIO_C.
This mode is the only state where the ADC can act as the master (set in register ADIFMD). In master mode, the
ADC can output SCK clocks at 256fS or 512fS.
During normal ADC operation, the system clock (SCK) is sourced within the PCM9211 (that is, either the DIR
SCK, or the oscillator circuit SCK). By running the ADC in Master mode, the ADC can operate from an external
SCK source (such as a DSP or PLL circuit), and provide BCK and LRCK to the rest of the PCM9211 circuitry and
external components.
To configure the ADC for standalone operation, set MPCSEL[2:0] to 001. ADIFMD should also be set to 010 or
100.
20
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): PCM9211
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