参数资料
型号: PH28F256L18B85
厂商: INTEL CORP
元件分类: PROM
英文描述: StrataFlash Wireless Memory
中文描述: 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79
封装: 0.75 MM PITCH, LEAD FREE, VFBGA-79
文件页数: 32/106页
文件大小: 1272K
代理商: PH28F256L18B85
Intel StrataFlash Wireless Memory (L18)
April 2005
32
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
7.5
AC Read Specifications for 256-Mbit Density (V
CCQ
= 1.7 V –
2.0 V)
Num
Symbol
Parameter
Speed
–85
Units
Notes
Min
Max
Asynchronous Specifications
R1
t
AVAV
Read cycle time
V
CC
= V
CCQ
= 1.8 V – 2.0 V
V
CC
= V
CCQ
= 1.7 V – 2.0 V
V
CC
= V
CCQ
= 1.8 V – 2.0 V
V
CC
= V
CCQ
= 1.7 V – 2.0 V
V
CC
= V
CCQ
= 1.8 V – 2.0 V
V
CC
= V
CCQ
= 1.7 V – 2.0 V
85
-
ns
6
88
-
R2
t
AVQV
Address to output valid
-
85
ns
-
88
R3
t
ELQV
CE# low to output valid
-
85
ns
-
88
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R15
R16
R17
t
GLQV
t
PHQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
OH
t
EHEL
t
ELTV
t
EHTZ
t
GLTV
t
GLTX
t
GHTZ
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
-
-
0
0
-
-
0
14
-
-
-
0
-
20
150
-
-
17
17
-
-
14
14
14
-
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1
1,3
1,2,3
1,3
1
1
1,3
1
1,3
1,3
Latching Specifications
R101
R102
t
AVVH
t
ELVH
Address setup to ADV# high
CE# low to ADV# high
7
-
-
ns
ns
1
10
-
R103
t
VLQV
ADV# low to output valid
V
CC
= V
CCQ
= 1.8 V – 2.0
V
CC
= V
CCQ
= 1.7 V – 2.0
85
ns
1,6
-
7
7
7
-
30
88
-
-
-
25
-
R104
R105
R106
R108
R111
t
VLVH
t
VHVL
t
VHAX
t
APA
t
phvh
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
ns
ns
ns
ns
ns
1
1,4
1
1
Clock Specifications
R200
R201
R202
R203
f
CLK
t
CLK
t
CH/CL
t
FCLK/RCLK
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
-
54
-
-
3
MHz
ns
ns
ns
1,3
18.5
3.5
-
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
t
AVCH/L
t
VLCH/L
t
ELCH/L
t
CHQV
/ t
CLQV
t
CHQX
t
CHAX
t
CHTV
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
7
7
7
-
3
7
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
1
14
-
-
14
1,5
1,4,5
1,5
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