- 您现在的位置：买卖IC网 > PDF目录367933 > PH28F256L18B85 (INTEL CORP) StrataFlash Wireless Memory PDF资料下载
参数资料
| 型号： | PH28F256L18B85 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79 |
| 封装： | 0.75 MM PITCH, LEAD FREE, VFBGA-79 |
| 文件页数： | 71/106页 |
| 文件大小： | 1272K |
| 代理商： | PH28F256L18B85 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页当前第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
71
14.0
Dual-Operation Considerations
The multi-partition architecture of the device allows background programming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
14.1
Memory Partitioning
The L18 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous
read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at
a time can be in program or erase mode.
The flash device supports read-while-write operations with
bus cycle granularity
and not command
granularity. In other words, it is
not
assumed that both bus cycles of a two cycle command (an erase
command for example) will always occur as back to back bus cycles to the flash device. In
practice, code fetches (reads) may be interspersed between write cycles to the flash device, and
they will likely be directed to a different partition than the one being written. This is especially true
when a processor is executing code from one partition that instructs the processor to program or
erase in another partition.
14.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write
command’s (
Figure 30
, and
Figure 31
). However, a write operation issued between a 2-cycle
commands write sequence causes a command sequence error. (See
Figure 32
)
When reading from the same partition after issuing a Setup command, Status Register data is
returned, regardless of the read mode of the partition prior to issuing the Setup command.
Figure 30.
Operating Mode with Correct Command Sequence Example
Partition A
Partition A
Partition B
0x20
0xD0
0xFF
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
相关PDF资料 |
PDF描述 |
|---|---|
| PH28F256L18T85 | StrataFlash Wireless Memory |
| PH28F640L18B85 | StrataFlash Wireless Memory |
| PH28F640L18T85 | StrataFlash Wireless Memory |
| PH2907A | PNP switching transistor |
| PH2907 | PNP switching transistor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PH28F256L18B85A | 制造商:Micron Technology Inc 功能描述:MM#875138FLASH 28F256L18B 85 VF-PBGA79 S |
| PH28F256L18T85 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| PH28F320C3TD70A | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 2M x 16 70ns 48-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:MM#869664FLASH 28F320C3TD 70 VF-PBGA47 E |
| PH28F320W18BE60A | 制造商:Micron Technology Inc 功能描述:IC FLASH 32MBIT 60NS VFBGA |
| PH28F320W18BE60B | 制造商:Micron Technology Inc 功能描述:32MB, CRYSTAL .75 VFBGA 1.8 LF - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。