- 您现在的位置：买卖IC网 > PDF目录367933 > PH28F256L18B85 (INTEL CORP) StrataFlash Wireless Memory PDF资料下载
参数资料
| 型号： | PH28F256L18B85 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79 |
| 封装： | 0.75 MM PITCH, LEAD FREE, VFBGA-79 |
| 文件页数： | 62/106页 |
| 文件大小： | 1272K |
| 代理商： | PH28F256L18B85 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页当前第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Intel StrataFlash Wireless Memory (L18)
April 2005
62
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
Data words from the write buffer are directed to sequential memory locations in the flash memory
array; programming continues from where the previous buffer sequence ended. The host
programming system must poll SR[0] to determine when the buffer program sequence completes.
SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set
indicates that the buffer is not available yet for the next fill cycle. The host system may check full
status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit. After
the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is
ready for the next buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal program is
proceeding.
The host programming system continues the Buffered EFP algorithm by providing the next group
of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the
block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block address;
data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the
Buffered EFP Exit phase.
11.3.4
Buffered EFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status check
should be performed on the partition being programmed at this time to ensure the entire block
programmed successfully. When exiting the Buffered EFP algorithm with a block address change,
the read mode of both the programmed and the addressed partition will not change. After Buffered
EFP exit, any valid command can be issued to the device.
11.4
Program Suspend
Issuing the Program Suspend command while programming suspends the programming operation.
This allows data to be accessed from memory locations other than the one being programmed. The
Program Suspend command can be issued to any device address; the corresponding partition is not
affected. A program operation can be suspended to perform reads only. Additionally, a program
operation that is running during an erase suspend can be suspended to perform a read operation
(see
Figure 40, “Program Suspend/Resume Flowchart” on page 86
).
When a programming operation is executing, issuing the Program Suspend command requests the
WSM to suspend the programming algorithm at predetermined points. The partition that is
suspended continues to output Status Register data after the Program Suspend command is issued.
Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified
in
Section 7.7, “Program and Erase Characteristics” on page 41
.
To read data from blocks within the suspended partition, the Read Array command must be issued
to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, and
Program Resume are valid commands during a program suspend.
A program operation does not need to be suspended in order to read data from a block in another
partition that is not programming. If the other partition is already in a Read Array, Read Device
Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other
partition is not in a read mode, one of the read commands must be issued to the partition before
data can be read.
相关PDF资料 |
PDF描述 |
|---|---|
| PH28F256L18T85 | StrataFlash Wireless Memory |
| PH28F640L18B85 | StrataFlash Wireless Memory |
| PH28F640L18T85 | StrataFlash Wireless Memory |
| PH2907A | PNP switching transistor |
| PH2907 | PNP switching transistor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PH28F256L18B85A | 制造商:Micron Technology Inc 功能描述:MM#875138FLASH 28F256L18B 85 VF-PBGA79 S |
| PH28F256L18T85 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| PH28F320C3TD70A | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 2M x 16 70ns 48-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:MM#869664FLASH 28F320C3TD 70 VF-PBGA47 E |
| PH28F320W18BE60A | 制造商:Micron Technology Inc 功能描述:IC FLASH 32MBIT 60NS VFBGA |
| PH28F320W18BE60B | 制造商:Micron Technology Inc 功能描述:32MB, CRYSTAL .75 VFBGA 1.8 LF - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。