参数资料
型号: PI7C8150BNDE
厂商: Pericom
文件页数: 63/109页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
标准包装: 90
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(17x17)
包装: 管件
安装类型: 表面贴装
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 57 of 109
April 2009 – Revision 1.08
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
1
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 6-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150B detects a parity
error on the secondary interface.
Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Secondary
Detected
Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 6-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
PI7C8150B must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Primary
Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
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