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参数资料
型号： PI7C8150BNDE
厂商： Pericom
文件页数： 94/109页
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 256-PBGA
标准包装： 90
系列： *
应用： *
接口： *
电源电压： *
封装/外壳： 256-BGA
供应商设备封装： 256-PBGA（17x17）
包装： 管件
安装类型： 表面贴装
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 85 of 109
April 2009 – Revision 1.08
Bit
Function
Type
Description
22
Secondary
Interface Reset
R/W
Controls the assertion of S_RESET_L signal pin on the secondary
interface
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
23
Fast Back-to-
Back Enable
R/W
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
24
Primary Master
Timeout
R/W
Set’s the maximum number of PCI clocks the bridge will wait for an
initiator on the primary to repeat a delayed transaction request. The
counter starts right after the delayed transaction is at the front of the
queue. If the master has not repeated at least once before the counter
expires, the bridge discards the transaction from the queue.
0: 2
15
PCI clocks
1: 2
10
PCI clocks
Reset to 0
25
Secondary
Master Timeout
R/W
Set’s the maximum number of PCI clocks the bridge will wait for an
initiator on the secondary to repeat a delayed transaction request. The
counter starts right after the delayed transaction is at the front of the
queue. If the master has not repeated at least once before the counter
expires, the bridge discards the transaction from the queue.
0: 2
15
PCI clocks
1: 2
10
PCI clocks
Reset to 0
26
Master Timeout
Status
R/WC
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
27
Discard Timer
P_SERR_L
enable
R/W
This bit is set to 1 and P_SERR_L is asserted when either the
primary discard timer or the secondary discard timer expire.
Reset to 0
31-28
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.29
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control
R/W
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
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相关代理商/技术参数
参数描述
PI7C8150BNDI 功能描述:外围驱动器与原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray
PI7C8150BNDI-33 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BNDIE 功能描述:外围驱动器与原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray
PI7C8150BNDIE-33 功能描述:外围驱动器与原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray
PI7C8150DMAE 功能描述:外围驱动器与原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray
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