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| 型号： | PI7C8150BNDE |
| 厂商： | Pericom |
| 文件页数： | 68/109页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 标准包装： | 90 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-PBGA（17x17） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 61 of 109
April 2009 – Revision 1.08
Delayed write data discarded after 2
24 (default) attempts to deliver (224 target retries
received)
Delayed read data cannot be transferred from target after 2
24 (default) attempts (224
target retries received)
Master timeout on delayed transaction
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion
for specific events. The master timeout condition has a SERR_L enable bit for that event in
the bridge control register and therefore does not have a device-specific disable bit.
7
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK_L signal to implement exclusive access to a
target for transactions that cross PI7C8150B.
7.1
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when
a locked transaction crosses PI7C8150B. A primary master can lock a primary target
without affecting the status of the lock on the secondary bus, and vice versa. This means
that a primary master can lock a primary target at the same time that a secondary master
locks a secondary target.
7.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B
For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions are
met:
The PCI bus must be idle.
The LOCK_L signal must be de-asserted.
The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts
LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target
lock has been achieved.
7.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
Locked transactions can cross PI7C8150B only in the downstream direction, from the
primary bus to the secondary bus.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8150BNDI | 功能描述:外围驱动器与原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150BNDI-33 | 制造商:PERICOM 制造商全称:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BNDIE | 功能描述:外围驱动器与原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150BNDIE-33 | 功能描述:外围驱动器与原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150DMAE | 功能描述:外围驱动器与原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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