参数资料
型号: PIC16C72-04E/SP
厂商: Microchip Technology
文件页数: 68/114页
文件大小: 0K
描述: IC MCU OTP 2KX14 A/D PWM 28DIP
标准包装: 15
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
数据转换器: A/D 5x8b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
1997 Microchip Technology Inc.
DS30390E-page 57
PIC16C7X
6.0
OVERVIEW OF TIMER
MODULES
The
PIC16C72,
PIC16C73/73A,
PIC16C74/74A,
PIC16C76/77 each have three timer modules.
Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer overow). Each of
these modules is explained in full detail in the following
sections. The timer modules are:
Timer0 Module (Section 7.0)
Timer1 Module (Section 8.0)
Timer2 Module (Section 9.0)
6.1
Timer0 Overview
The Timer0 module is a simple 8-bit overow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock. When the clock
source is an external clock, the Timer0 module can be
selected to increment on either the rising or falling
edge.
The Timer0 module also has a programmable pres-
caler option. This prescaler can be assigned to either
the Timer0 module or the Watchdog Timer. Bit PSA
(OPTION<3>) assigns the prescaler, and bits PS2:PS0
(OPTION<2:0>) determine the prescaler value. Timer0
can increment at the following rates: 1:1 (when pres-
caler assigned to Watchdog timer), 1:2, 1:4, 1:8, 1:16,
1:32, 1:64, 1:128, and 1:256 (Timer0 only).
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre-
quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
6.2
Timer1 Overview
Timer1 is a 16-bit timer/counter. The clock source can
be either the internal system clock (Fosc/4), an external
clock, or an external crystal. Timer1 can operate as
either a timer or a counter. When operating as a
counter (external clock source), the counter can either
operate synchronized to the device or asynchronously
to the device. Asynchronous operation allows Timer1 to
operate during sleep, which is useful for applications
that require a real-time clock as well as the power sav-
ings of SLEEP mode.
Timer1 also has a prescaler option which allows
Timer1 to increment at the following rates: 1:1, 1:2, 1:4,
and 1:8. Timer1 can be used in conjunction with the
Capture/Compare/PWM module. When used with a
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
CCP module, Timer1 is the time-base for 16-bit Cap-
ture or the 16-bit Compare and must be synchronized
to the device.
6.3
Timer2 Overview
Timer2 is an 8-bit timer with a programmable prescaler
and postscaler, as well as an 8-bit period register
(PR2). Timer2 can be used with the CCP1 module (in
PWM mode) as well as the Baud Rate Generator for
the Synchronous Serial Port (SSP). The prescaler
option allows Timer2 to increment at the following
rates: 1:1, 1:4, 1:16.
The postscaler allows the TMR2 register to match the
period register (PR2) a programmable number of times
before generating an interrupt. The postscaler can be
programmed from 1:1 to 1:16 (inclusive).
6.4
CCP Overview
The CCP module(s) can operate in one of these three
modes: 16-bit capture, 16-bit compare, or up to 10-bit
Pulse Width Modulation (PWM).
Capture mode captures the 16-bit value of TMR1 into
the CCPRxH:CCPRxL register pair. The capture event
can be programmed for either the falling edge, rising
edge, fourth rising edge, or the sixteenth rising edge of
the CCPx pin.
Compare mode compares the TMR1H:TMR1L register
pair to the CCPRxH:CCPRxL register pair. When a
match occurs an interrupt can be generated, and the
output pin CCPx can be forced to given state (High or
Low), TMR1 can be reset (CCP1), or TMR1 reset and
start A/D conversion (CCP2). This depends on the con-
trol bits CCPxM3:CCPxM0.
PWM mode compares the TMR2 register to a 10-bit
duty cycle register (CCPRxH:CCPRxL<5:4>) as well as
to an 8-bit period register (PR2). When the TMR2 reg-
ister = Duty Cycle register, the CCPx pin will be forced
low. When TMR2 = PR2, TMR2 is cleared to 00h, an
interrupt can be generated, and the CCPx pin (if an out-
put) will be forced high.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
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