
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
90
6.4
Output timing delays assume a capacitive loading of 30 pF on SE_D_OUT(3:0,3:0) and 48 pF on
SE_SOC_OUT. Figure 62 shows the bit-level timing for the QRT..
QRT-QSE Interface Timing
Figure 62. QRT Bit-Level Timing
Symbol
Parameter
Signals
Min
Max
Unit
Fseclk**
Frequency of SE_CLK
SE_CLK
65.4
68
MHz
clock duty cycle
SE_CLK
40
60
%
<10 KHz Jitter tolerance *
BP_ACK_IN(3:0), SE_SOC_IN(3:0)
2
clock
period
>10 KHz Jitter tolerance *
BP_ACK_IN(3:0), SE_SOC_IN(3:0)
0.35
clock
period
Tctsu
Control signal setup time
RX_CELL_START
1.5
ns
Tctho
Control signal hold time
RX_CELL_START
0
ns
Tsesu*
Setup time before SE_CLK
SE_D_IN(3:0,3:0), SE_SOC_IN(3:0),
BP_ACK_IN(3:0)
4.0
ns
Tseho*
Hold time after SE_CLK
SE_D_IN(3:0,3:0), SE_SOC_IN(3:0),
BP_ACK_IN(3:0)
1.5
ns
Tseq
Output delay from SE_CLK
SE_D_OUT(3:0,3:0),
BP_ACK_OUT(3:0), SE_SOC_OUT
2.9
10.0
ns
Output delay skew *
SE_D_OUT(0,3:0) and SE_SOC_OUT
SE_D_OUT(1,3:0) and SE_SOC_OUT
SE_D_OUT(2,3:0) and SE_SOC_OUT
SE_D_OUT(3,3:0) and SE_SOC_OUT
1.3
ns
Input delay skew *
SE_D_IN(0,3:0) and SE_SOC_IN(0)
SE_D_IN(1,3:0) and SE_SOC_IN(1)
SE_D_IN(2,3:0) and SE_SOC_IN(2)
SE_D_IN(3,3:0) and SE_SOC_IN(3)
3
ns
Tctsu
Tsesu
Fseclk
Tseho
Tseq
Tctho
Tseq
SE_CLK
SE_D_IN(3:0,3:0), BP_ACK_IN(3:0)
SE_D_OUT(3:0,3:0), BP_ACK_OUT(3:0)
RX_CELL_START
SE_SOC_OUT