
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
169
8.5.5
RX_RSF_ER_CELL_PTR (Internal Structure)
Offset: 20
h
(80
h
byte)
Type: Read/Write – Do not write while SW_RESET (refer to
“SW_RESET” on
page 101
) is deasserted.
Format: Refer to the following table.
8.6
Transmit Switch Fabric Control RAM (TSF_CONTROL_RAM) Summary
NOTE: All registers in this RAM contain state information. No configuration or initialization is necessary.
The only foreseen uses for this information are in system- and board-level diagnostics and/or debug.
8.6.1
TX_TSF_SN_CHAN (Internal Structure)
Base address: 140000
h
(500000
h
byte)
Index: 1
h
Number of entries: 12
Type: Read-only
Long address = 140000
h
+
TSF_buffer_number
Byte address = 500000
h
+ 4
×
TSF_buffer_number
Format: Refer to the following table.
RX_RSF_CHAN
(13:0)
The receive channel number from which this cell originated.
Field (Bits)
Description
RX_RSF_ER
(31:16)
The ER value to be sent in the payload of this cell pending RSF transmission if it is an
RM cell.
RX_RSF_CELL_PTR
(15:0)
The cell pointer address of the cell pending, or that has completed, RSF transmission.
Field (Bits)
Description
Not present
(31:28)
RAM is not present in these bit locations.
TX_TSF_CLP_PTI
(27:24)
The CLP and PTI for the cell received from the Transmit Switch Fabric (TSF).
Not used
(23:22)
Driven with a 0. Mask on reads to maintain software compatibility with future versions.
TX_TSF_SN
(21:16)
The sequence number of the cell received from the TSF.
TX_TSF_OUTCHAN
(15:0)
The transmit OUTCHAN channel number of the cell received from the TSF.
(Continued)
Field (Bits)
Description